📄 elec_lock.rpt
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(18) 21 B DFFE t 0 0 0 0 2 0 1 |debouncing:U2|dff2
- 22 B DFFE t 0 0 0 0 2 0 7 |debouncing:U2|d0 (|debouncing:U2|:8)
(4) 16 A DFFE t 0 0 0 0 2 0 6 |debouncing:U2|d1 (|debouncing:U2|:9)
(17) 24 B DFFE t 0 0 0 1 1 0 1 |debouncing:U3|dff1
- 28 B DFFE t 0 0 0 0 2 0 1 |debouncing:U3|dff2
- 29 B DFFE t 0 0 0 0 2 0 7 |debouncing:U3|d0 (|debouncing:U3|:8)
- 15 A DFFE t 0 0 0 0 2 0 6 |debouncing:U3|d1 (|debouncing:U3|:9)
- 13 A TFFE + t 0 0 0 0 4 4 6 Q4 (:30)
- 9 A TFFE + t 0 0 0 0 3 4 7 Q3 (:31)
- 12 A TFFE + t 0 0 0 0 2 0 2 Q2 (:32)
- 23 B TFFE + t 0 0 0 0 1 0 3 Q1 (:33)
(21) 17 B TFFE + t 0 0 0 0 0 1 38 Q0 (:34)
(11) 3 A DFFE t 5 3 0 0 9 0 16 N3 (:61)
- 6 A DFFE t 4 3 1 0 9 0 16 N2 (:62)
- 7 A DFFE t 4 3 1 0 9 0 16 N1 (:63)
(12) 1 A DFFE t 4 3 1 0 9 0 16 N0 (:64)
- 2 A DFFE t 1 0 1 0 9 1 16 F2 (:66)
- 10 A DFFE t 1 0 1 0 9 1 0 F0 (:68)
- 27 B DFFE t 1 1 0 0 5 0 2 ACC15 (:71)
- 26 B DFFE t 1 1 0 0 5 0 2 ACC14 (:72)
- 63 D DFFE t 1 1 0 0 5 0 2 ACC13 (:73)
(13) 32 B DFFE t 1 1 0 0 5 0 2 ACC12 (:74)
- 18 B DFFE t 1 1 0 0 5 0 3 ACC11 (:75)
(24) 33 C DFFE t 1 1 0 0 5 0 3 ACC10 (:76)
- 47 C DFFE t 1 1 0 0 5 0 4 ACC9 (:77)
- 34 C DFFE t 1 1 0 0 5 0 3 ACC8 (:78)
- 38 C DFFE t 1 1 0 0 5 0 3 ACC7 (:79)
- 39 C DFFE t 1 1 0 0 5 0 3 ACC6 (:80)
(41) 64 D DFFE t 1 1 0 0 5 0 3 ACC5 (:81)
- 55 D DFFE t 1 1 0 0 5 0 4 ACC4 (:82)
(32) 48 C DFFE t 1 1 0 0 4 0 3 ACC3 (:83)
(31) 46 C DFFE t 1 1 0 0 4 0 3 ACC2 (:84)
- 45 C DFFE t 1 1 0 0 4 0 3 ACC1 (:85)
- 43 C DFFE t 1 1 0 0 4 0 3 ACC0 (:86)
- 61 D TFFE t 0 0 0 0 5 0 2 REG15 (:87)
(40) 62 D TFFE t 0 0 0 0 5 0 2 REG14 (:88)
(38) 56 D TFFE t 0 0 0 0 5 0 2 REG13 (:89)
- 54 D TFFE t 0 0 0 0 5 0 2 REG12 (:90)
(37) 53 D TFFE t 0 0 0 0 5 0 2 REG11 (:91)
(36) 52 D TFFE t 0 0 0 0 5 0 2 REG10 (:92)
(33) 49 D TFFE t 0 0 0 0 5 0 3 REG9 (:93)
- 50 D TFFE t 0 0 0 0 5 0 2 REG8 (:94)
(34) 51 D TFFE t 0 0 0 0 5 0 2 REG7 (:95)
(29) 41 C TFFE t 0 0 0 0 5 0 2 REG6 (:96)
(26) 36 C TFFE t 0 0 0 0 5 0 2 REG5 (:97)
(27) 37 C TFFE t 0 0 0 0 5 0 3 REG4 (:98)
(25) 35 C TFFE t 0 0 0 0 5 0 2 REG3 (:99)
- 44 C TFFE t 0 0 0 0 5 0 2 REG2 (:100)
- 60 D TFFE t 0 0 0 0 5 0 2 REG1 (:101)
- 59 D TFFE t 0 0 0 0 5 0 2 REG0 (:102)
- 58 D SOFT s t 14 0 1 0 21 1 0 ~1229~1
- 42 C SOFT s t 1 0 1 0 6 0 1 ~1229~2
(28) 40 C SOFT s t 1 0 1 0 6 0 1 ~1229~3
(39) 57 D SOFT s t 1 0 1 0 6 0 1 ~1229~4
Code:
s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: f:\test1_last\elec_lock.rpt
elec_lock
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'A':
Logic cells placed in LAB 'A'
+------------------------------- LC4 CLK_SCAN0
| +----------------------------- LC5 CLK_SCAN1
| | +--------------------------- LC11 CLK_SCAN2
| | | +------------------------- LC14 CLK_SCAN3
| | | | +----------------------- LC8 |debouncing:U1|d1
| | | | | +--------------------- LC16 |debouncing:U2|d1
| | | | | | +------------------- LC15 |debouncing:U3|d1
| | | | | | | +----------------- LC13 Q4
| | | | | | | | +--------------- LC9 Q3
| | | | | | | | | +------------- LC12 Q2
| | | | | | | | | | +----------- LC3 N3
| | | | | | | | | | | +--------- LC6 N2
| | | | | | | | | | | | +------- LC7 N1
| | | | | | | | | | | | | +----- LC1 N0
| | | | | | | | | | | | | | +--- LC2 F2
| | | | | | | | | | | | | | | +- LC10 F0
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'A'
LC | | | | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'A':
LC8 -> - - - - - - - - - - * * * * * * | * - - - | <-- |debouncing:U1|d1
LC16 -> - - - - - - - - - - * * * * * * | * - - - | <-- |debouncing:U2|d1
LC15 -> - - - - - - - - - - * * * * * * | * - - - | <-- |debouncing:U3|d1
LC13 -> * * * * - - - * - - * * * * * * | * - - - | <-- Q4
LC9 -> * * * * - - - * * - * * * * * * | * - - - | <-- Q3
LC12 -> - - - - - - - * * * - - - - - - | * - - - | <-- Q2
Pin
43 -> - - - - - - - - - - - - - - - - | - - - - | <-- CLK_4M
LC19 -> - - - - * - - - - - * * * * * * | * - - - | <-- |debouncing:U1|d0
LC22 -> - - - - - * - - - - * * * * * * | * - - - | <-- |debouncing:U2|d0
LC29 -> - - - - - - * - - - * * * * * * | * - - - | <-- |debouncing:U3|d0
LC23 -> - - - - - - - * * * - - - - - - | * - - - | <-- Q1
LC17 -> - - - - * * * * * * * * * * * * | * * * * | <-- Q0
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: f:\test1_last\elec_lock.rpt
elec_lock
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+------------------------------- LC31 |debouncing:U1|dff1
| +----------------------------- LC30 |debouncing:U1|dff2
| | +--------------------------- LC19 |debouncing:U1|d0
| | | +------------------------- LC20 |debouncing:U2|dff1
| | | | +----------------------- LC21 |debouncing:U2|dff2
| | | | | +--------------------- LC22 |debouncing:U2|d0
| | | | | | +------------------- LC24 |debouncing:U3|dff1
| | | | | | | +----------------- LC28 |debouncing:U3|dff2
| | | | | | | | +--------------- LC29 |debouncing:U3|d0
| | | | | | | | | +------------- LC25 ENLOCK
| | | | | | | | | | +----------- LC23 Q1
| | | | | | | | | | | +--------- LC17 Q0
| | | | | | | | | | | | +------- LC27 ACC15
| | | | | | | | | | | | | +----- LC26 ACC14
| | | | | | | | | | | | | | +--- LC32 ACC12
| | | | | | | | | | | | | | | +- LC18 ACC11
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'B':
LC31 -> - * - - - - - - - - - - - - - - | - * - - | <-- |debouncing:U1|dff1
LC30 -> - - * - - - - - - - - - - - - - | - * - - | <-- |debouncing:U1|dff2
LC20 -> - - - - * - - - - - - - - - - - | - * - - | <-- |debouncing:U2|dff1
LC21 -> - - - - - * - - - - - - - - - - | - * - - | <-- |debouncing:U2|dff2
LC24 -> - - - - - - - * - - - - - - - - | - * - - | <-- |debouncing:U3|dff1
LC28 -> - - - - - - - - * - - - - - - - | - * - - | <-- |debouncing:U3|dff2
LC25 -> - - - - - - - - - * - - - - - - | - * * * | <-- ENLOCK
LC17 -> * * * * * * * * * * * * - - - - | * * * * | <-- Q0
LC18 -> - - - - - - - - - - - - * - - - | - * - * | <-- ACC11
Pin
43 -> - - - - - - - - - - - - - - - - | - - - - | <-- CLK_4M
11 -> * - - - - - - - - - - - - - - - | - * - - | <-- KEY_IN0
12 -> - - - * - - - - - - - - - - - - | - * - - | <-- KEY_IN1
14 -> - - - - - - * - - - - - - - - - | - * - - | <-- KEY_IN2
LC3 -> - - - - - - - - - - - - * * * * | - * * * | <-- N3
LC6 -> - - - - - - - - - - - - * * * * | - * * * | <-- N2
LC7 -> - - - - - - - - - - - - * * * * | - * * * | <-- N1
LC1 -> - - - - - - - - - - - - * * * * | - * * * | <-- N0
LC2 -> - - - - - - - - - * - - - - - - | - * * * | <-- F2
LC10 -> - - - - - - - - - * - - - - - - | - * - - | <-- F0
LC33 -> - - - - - - - - - - - - - * - - | - * - * | <-- ACC10
LC34 -> - - - - - - - - - - - - - - * - | - * - * | <-- ACC8
LC38 -> - - - - - - - - - - - - - - - * | - * - * | <-- ACC7
LC58 -> - - - - - - - - - * - - - - - - | - * - - | <-- ~1229~1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: f:\test1_last\elec_lock.rpt
elec_lock
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'C':
Logic cells placed in LAB 'C'
+------------------------------- LC33 ACC10
| +----------------------------- LC47 ACC9
| | +--------------------------- LC34 ACC8
| | | +------------------------- LC38 ACC7
| | | | +----------------------- LC39 ACC6
| | | | | +--------------------- LC48 ACC3
| | | | | | +------------------- LC46 ACC2
| | | | | | | +----------------- LC45 ACC1
| | | | | | | | +--------------- LC43 ACC0
| | | | | | | | | +------------- LC41 REG6
| | | | | | | | | | +----------- LC36 REG5
| | | | | | | | | | | +--------- LC37 REG4
| | | | | | | | | | | | +------- LC35 REG3
| | | | | | | | | | | | | +----- LC44 REG2
| | | | | | | | | | | | | | +--- LC42 ~1229~2
| | | | | | | | | | | | | | | +- LC40 ~1229~3
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'C'
LC | | | | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'C':
LC39 -> * - - - - - - - - * - - - - - * | - - * - | <-- ACC6
LC48 -> - - - * - - - - - - - - * - * - | - - * - | <-- ACC3
LC46 -> - - - - * - - - - - - - - * * - | - - * - | <-- ACC2
LC41 -> - - - - - - - - - * - - - - - * | - - * - | <-- REG6
LC36 -> - - - - - - - - - - * - - - - * | - - * - | <-- REG5
LC37 -> - - - - - - - - - - - * - - * * | - - * - | <-- REG4
LC35 -> - - - - - - - - - - - - * - * - | - - * - | <-- REG3
LC44 -> - - - - - - - - - - - - - * * - | - - * - | <-- REG2
Pin
43 -> - - - - - - - - - - - - - - - - | - - - - | <-- CLK_4M
LC25 -> - - - - - - - - - * * * * * - - | - * * * | <-- ENLOCK
LC17 -> - - - - - - - - - * * * * * - - | * * * * | <-- Q0
LC3 -> * * * * * * * * * - - - - - - - | - * * * | <-- N3
LC6 -> * * * * * * * * * - - - - - - - | - * * * | <-- N2
LC7 -> * * * * * * * * * - - - - - - - | - * * * | <-- N1
LC1 -> * * * * * * * * * - - - - - - - | - * * * | <-- N0
LC2 -> - - - - - - - - - * * * * * - - | - * * * | <-- F2
LC64 -> - * - - - - - - - - * - - - - * | - - * - | <-- ACC5
LC55 -> - - * - - - - - - - - * - - * * | - - * - | <-- ACC4
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: f:\test1_last\elec_lock.rpt
elec_lock
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'D':
Logic cells placed in LAB 'D'
+------------------------------- LC63 ACC13
| +----------------------------- LC64 ACC5
| | +--------------------------- LC55 ACC4
| | | +------------------------- LC61 REG15
| | | | +----------------------- LC62 REG14
| | | | | +--------------------- LC56 REG13
| | | | | | +------------------- LC54 REG12
| | | | | | | +----------------- LC53 REG11
| | | | | | | | +--------------- LC52 REG10
| | | | | | | | | +------------- LC49 REG9
| | | | | | | | | | +----------- LC50 REG8
| | | | | | | | | | | +--------- LC51 REG7
| | | | | | | | | | | | +------- LC60 REG1
| | | | | | | | | | | | | +----- LC59 REG0
| | | | | | | | | | | | | | +--- LC58 ~1229~1
| | | | | | | | | | | | | | | +- LC57 ~1229~4
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'D'
LC | | | | | | | | | | | | | | | | | A B C D | Logic cells that feed LAB 'D':
LC63 -> - - - - - * - - - - - - - - * - | - - - * | <-- ACC13
LC61 -> - - - * - - - - - - - - - - * - | - - - * | <-- REG15
LC62 -> - - - - * - - - - - - - - - * - | - - - * | <-- REG14
LC56 -> - - - - - * - - - - - - - - * - | - - - * | <-- REG13
LC54 -> - - - - - - * - - - - - - - * - | - - - * | <-- REG12
LC53 -> - - - - - - - * - - - - - - * - | - - - * | <-- REG11
LC52 -> - - - - - - - - * - - - - - * - | - - - * | <-- REG10
LC49 -> - - - - - - - - - * - - - - * * | - - - * | <-- REG9
LC50 -> - - - - - - - - - - * - - - - * | - - - * | <-- REG8
LC51 -> - - - - - - - - - - - * - - - * | - - - * | <-- REG7
LC60 -> - - - - - - - - - - - - * - * - | - - - * | <-- REG1
LC59 -> - - - - - - - - - - - - - * * - | - - - * | <-- REG0
LC57 -> - - - - - - - - - - - - - - * - | - - - * | <-- ~1229~4
Pin
43 -> - - - - - - - - - - - - - - - - | - - - - | <-- CLK_4M
LC25 -> - - - * * * * * * * * * * * - - | - * * * | <-- ENLOCK
LC17 -> - - - * * * * * * * * * * * - - | * * * * | <-- Q0
LC3 -> * * * - - - - - - - - - - - - - | - * * * | <-- N3
LC6 -> * * * - - - - - - - - - - - - - | - * * * | <-- N2
LC7 -> * * * - - - - - - - - - - - - - | - * * * | <-- N1
LC1 -> * * * - - - - - - - - - - - - - | - * * * | <-- N0
LC2 -> - - - * * * * * * * * * * * - - | - * * * | <-- F2
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