debouncing.vhd

来自「vhdl代码写的一个密码锁程序」· VHDL 代码 · 共 37 行

--防抖模块
LIBRARY ieee;  
USE ieee.std_logic_1164.ALL;  
  
LIBRARY altera;  
USE altera.maxplus2.ALL;  
  
ENTITY debouncing IS  
     PORT  
     (  
         d_in, clk     : IN   STD_LOGIC;  
         d_out         : OUT  STD_LOGIC   
     );  
END debouncing ;  
  
ARCHITECTURE a OF debouncing IS  
signal  vcc, inv_d : std_logic ;  
signal  q0, q1  : std_logic ;   
signal  d1, d0  : std_logic ;   
  
BEGIN  
    vcc <= '1' ;  
    inv_d <= not d_in ;  
    dff1 : dff PORT MAP (d =>vcc , q => q0 , clk => clk, clrn =>inv_d , prn => vcc);  
    dff2 : dff PORT MAP (d =>vcc , q => q1, clk => clk, clrn => q0 , prn => vcc);  
  
process (clk)  
begin  
     if clk'event and clk='1' then  
           d0 <= not q1;    
           d1 <= d0; 
     end if ;  
end process ;  
d_out <= not (d1 and not d0);  
 
END a;