bit_synchronous.vhd

用一片CPLD实现数字锁相环,用VHDL或V语言.

--PLL    2006.12.17
library  IEEE;
use IEEE.std_logic_1164.all;                
use IEEE.std_logic_unsigned.all;            
entity bit_synchronous is                    
 port (                                   
clock:    in  STD_LOGIC;      --D接12MHz时钟，本地振荡频率。      
   fb:    in  STD_LOGIC;       --D接板上256Hz时钟，接收码元时钟频率
en_clock:  in  STD_LOGIC;     --    ――时钟使能，同步开始键
code_sel:  in  STD_LOGIC;       --   ――选择256b/s的翻转码或m序列
 fast:    in  STD_LOGIC;          --选择快同步或慢同步 
bit_sync: out  STD_LOGIC;       --D同步抽样脉冲输出
code256:  buffer  STD_LOGIC     --256Bb/s的翻转码输出或256b/s的m序列输出
);
end bit_synchronous;

architecture bit_synchronous_arch of bit_synchronous is
signal   clk_480KHz,bit_pulse:STD_LOGIC;
signal   q,fangbo,clk1,clk2:STD_LOGIC;
signal   count1875,preset1875:STD_LOGIC_VECTOR(10 DOWNTO 0);
signal   m: STD_LOGIC_VECTOR(2 DOWNTO 0);         --m序列
signal   count25: STD_LOGIC_VECTOR(4 DOWNTO 0);    --模25计数器


begin

clk1<=clock and en_clock;
clk2<=fb and en_clock;

m_sequence_form:                                  --产生"1110010"m序列
process(clk2)
begin
  if(clk2'event and clk2='1') then
m(0)<=m(1);
m(1)<=m(2);
end if;
end process;
--//////////////////////////////////////////
process(clk2)
begin
 if(clk2'event and clk2='1') then
   fangbo<=not fangbo;
m(2)<=(m(1)  xor  m(0)) or (not  (m(0)  or  m(1)  or  m(2)));
end if;
end process;

code256<=(code_sel  and  m(0))  or  ((not  code_sel)  and  fangbo);    --m序列输出

GET_480kHz:                      --12MHz 25分频得480kHz（再分频1875即可得到256Hz）
process(clk1)
begin
  if(clk1'event and clk1='1') then
  if(count25="11000") then count25<="00000";
else count25<=count25+'1';
end if;
clk_480kHz<=count25(0) or count25(1) or count25(2)  or count25(3)  or count25(4);
end if;
end process;


bit_pulse_extrive:                                     --从接收码元中提取位基准脉冲
process(clk1)
begin
  if(clk1'event and clk1='1') then
    q<=code256;
    bit_pulse<=code256 xor q;
  end if;
end process;


bit_sync_pulse_form:                                 --可预置分频器，产生位同步脉冲
process(clk_480kHz)
begin
  if(clk_480kHz'event and clk_480kHz='1') then
    if(count1875="00000000000") then count1875<=preset1875;
    else count1875<=count1875-'1';
    end if;
    if(count1875<"00000111111") then bit_sync<='1';
    else bit_sync<='0';
    end if;
  end if;
end process;


modify_preset_value:           --修改可预置分频器的预置值，从而调整位同步脉冲的相位
process(bit_pulse)
begin
  if(bit_pulse'event and bit_pulse='1') then
    if(count1875<"01110101000") then
      if(fast='1') then preset1875<="11101011011";  
      else preset1875<="11101010011";
      end if;
    elsif(count1875>"01110101010") then
      if(fast='1') then preset1875<="11101001001";
      else preset1875<="11101010001";
      end if;
    else preset1875<="11101010010";
    end if;
 end if;
 end process;
end bit_synchronous_arch;