111.map.qmsg

用一片CPLD实现数字锁相环,用VHDL或V语言.

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Feb 14 16:53:03 2007 " "Info: Processing started: Wed Feb 14 16:53:03 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off 111 -c 111 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off 111 -c 111" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "bit_synchronous.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file bit_synchronous.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 bit_synchronous-bit_synchronous_arch " "Info: Found design unit 1: bit_synchronous-bit_synchronous_arch" {  } { { "bit_synchronous.vhd" "" { Text "D:/so2006/cpld-pro/quartus4.1/PLL1218/bit_synchronous.vhd" 17 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 bit_synchronous " "Info: Found entity 1: bit_synchronous" {  } { { "bit_synchronous.vhd" "" { Text "D:/so2006/cpld-pro/quartus4.1/PLL1218/bit_synchronous.vhd" 5 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Error" "EVRFX_VHDL_IS_NOT_DECLARED" "clk_480kHz bit_synchronous.vhd(48) " "Error (10482): VHDL error at bit_synchronous.vhd(48): object \"clk_480kHz\" is used but not declared" {  } { { "bit_synchronous.vhd" "" { Text "D:/so2006/cpld-pro/quartus4.1/PLL1218/bit_synchronous.vhd" 48 0 0 } }  } 0 10482 "VHDL error at %2!s!: object \"%1!s!\" is used but not declared" 0 0}
{ "Error" "EVRFX_VHDL_UNIT_INGONRED_ERR" "bit_synchronous_arch bit_synchronous.vhd(17) " "Error (10523): Ignored construct bit_synchronous_arch at bit_synchronous.vhd(17) due to previous errors" {  } { { "bit_synchronous.vhd" "" { Text "D:/so2006/cpld-pro/quartus4.1/PLL1218/bit_synchronous.vhd" 17 0 0 } }  } 0 10523 "Ignored construct %1!s! at %2!s! due to previous errors" 0 0}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 2 s 0 s Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 2 errors, 0 warnings" { { "Error" "EQEXE_END_BANNER_TIME" "Wed Feb 14 16:53:03 2007 " "Error: Processing ended: Wed Feb 14 16:53:03 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:01 " "Error: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}