dpll.tan.summary

用一片CPLD实现数字锁相环,用VHDL或V语言.

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 4.910 ns
From           : signal_in
To             : delclk
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 11.803 ns
From           : signal_out~reg0
To             : signal_out
From Clock     : clk
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -2.495 ns
From           : signal_in
To             : dpout_delay
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : 138.48 MHz ( period = 7.221 ns )
From           : signal_out~reg0
To             : delclk
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Clock Setup: 'reset'
Slack          : N/A
Required Time  : None
Actual Time    : 369.41 MHz ( period = 2.707 ns )
From           : cnt_N[0]
To             : signal_out~reg0
From Clock     : reset
To Clock       : reset
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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