dpll.map.qmsg

用一片CPLD实现数字锁相环,用VHDL或V语言.

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Mar 20 22:11:11 2007 " "Info: Processing started: Tue Mar 20 22:11:11 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off dpll -c dpll " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off dpll -c dpll" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "dpll.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file dpll.v" { { "Info" "ISGN_ENTITY_NAME" "1 dpll " "Info: Found entity 1: dpll" {  } { { "dpll.v" "" { Text "D:/so2007/cpld_pro/DPLL2007/DPLL0227+V+qt6/dpll.v" 2 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "dpll " "Info: Elaborating entity \"dpll\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 9 dpll.v(46) " "Warning (10230): Verilog HDL assignment warning at dpll.v(46): truncated value with size 32 to match size of target (9)" {  } { { "dpll.v" "" { Text "D:/so2007/cpld_pro/DPLL2007/DPLL0227+V+qt6/dpll.v" 46 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 9 dpll.v(51) " "Warning (10230): Verilog HDL assignment warning at dpll.v(51): truncated value with size 32 to match size of target (9)" {  } { { "dpll.v" "" { Text "D:/so2007/cpld_pro/DPLL2007/DPLL0227+V+qt6/dpll.v" 51 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 dpll.v(83) " "Warning (10230): Verilog HDL assignment warning at dpll.v(83): truncated value with size 32 to match size of target (8)" {  } { { "dpll.v" "" { Text "D:/so2007/cpld_pro/DPLL2007/DPLL0227+V+qt6/dpll.v" 83 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 dpll.v(92) " "Warning (10230): Verilog HDL assignment warning at dpll.v(92): truncated value with size 32 to match size of target (8)" {  } { { "dpll.v" "" { Text "D:/so2007/cpld_pro/DPLL2007/DPLL0227+V+qt6/dpll.v" 92 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 dpll.v(99) " "Warning (10230): Verilog HDL assignment warning at dpll.v(99): truncated value with size 32 to match size of target (8)" {  } { { "dpll.v" "" { Text "D:/so2007/cpld_pro/DPLL2007/DPLL0227+V+qt6/dpll.v" 99 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 dpll.v(102) " "Warning (10230): Verilog HDL assignment warning at dpll.v(102): truncated value with size 32 to match size of target (8)" {  } { { "dpll.v" "" { Text "D:/so2007/cpld_pro/DPLL2007/DPLL0227+V+qt6/dpll.v" 102 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 dpll.v(124) " "Warning (10230): Verilog HDL assignment warning at dpll.v(124): truncated value with size 32 to match size of target (3)" {  } { { "dpll.v" "" { Text "D:/so2007/cpld_pro/DPLL2007/DPLL0227+V+qt6/dpll.v" 124 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 3 dpll.v(130) " "Warning (10230): Verilog HDL assignment warning at dpll.v(130): truncated value with size 32 to match size of target (3)" {  } { { "dpll.v" "" { Text "D:/so2007/cpld_pro/DPLL2007/DPLL0227+V+qt6/dpll.v" 130 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 9 dpll.v(161) " "Warning (10230): Verilog HDL assignment warning at dpll.v(161): truncated value with size 32 to match size of target (9)" {  } { { "dpll.v" "" { Text "D:/so2007/cpld_pro/DPLL2007/DPLL0227+V+qt6/dpll.v" 161 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 9 dpll.v(164) " "Warning (10230): Verilog HDL assignment warning at dpll.v(164): truncated value with size 32 to match size of target (9)" {  } { { "dpll.v" "" { Text "D:/so2007/cpld_pro/DPLL2007/DPLL0227+V+qt6/dpll.v" 164 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "addclk data_in GND " "Warning: Reduced register \"addclk\" with stuck data_in port to stuck value GND" {  } { { "dpll.v" "" { Text "D:/so2007/cpld_pro/DPLL2007/DPLL0227+V+qt6/dpll.v" 13 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "100 " "Info: Implemented 100 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "3 " "Info: Implemented 3 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "2 " "Info: Implemented 2 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "95 " "Info: Implemented 95 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 11 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 11 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 20 22:11:48 2007 " "Info: Processing ended: Tue Mar 20 22:11:48 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:37 " "Info: Elapsed time: 00:00:37" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}