dpll.tan.qmsg

用一片CPLD实现数字锁相环,用VHDL或V语言.

{ "Info" "ITDB_FULL_TCO_RESULT" "clk signal_out signal_out~reg0 11.803 ns register " "Info: tco from clock \"clk\" to destination pin \"signal_out\" through register \"signal_out~reg0\" is 11.803 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 6.994 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 6.994 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 32 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 32; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dpll.v" "" { Text "D:/so2007/cpld_pro/DPLL2007/DPLL0227+V+qt6/dpll.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.689 ns) + CELL(0.698 ns) 3.215 ns cnt8\[2\] 2 REG LC_X1_Y17_N5 4 " "Info: 2: + IC(1.689 ns) + CELL(0.698 ns) = 3.215 ns; Loc. = LC_X1_Y17_N5; Fanout = 4; REG Node = 'cnt8\[2\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.387 ns" { clk cnt8[2] } "NODE_NAME" } } { "dpll.v" "" { Text "D:/so2007/cpld_pro/DPLL2007/DPLL0227+V+qt6/dpll.v" 111 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.427 ns) + CELL(0.183 ns) 3.825 ns add_del_clkout~8 3 COMB LC_X1_Y17_N8 10 " "Info: 3: + IC(0.427 ns) + CELL(0.183 ns) = 3.825 ns; Loc. = LC_X1_Y17_N8; Fanout = 10; COMB Node = 'add_del_clkout~8'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.610 ns" { cnt8[2] add_del_clkout~8 } "NODE_NAME" } } { "dpll.v" "" { Text "D:/so2007/cpld_pro/DPLL2007/DPLL0227+V+qt6/dpll.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.627 ns) + CELL(0.542 ns) 6.994 ns signal_out~reg0 4 REG LC_X41_Y21_N9 5 " "Info: 4: + IC(2.627 ns) + CELL(0.542 ns) = 6.994 ns; Loc. = LC_X41_Y21_N9; Fanout = 5; REG Node = 'signal_out~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.169 ns" { add_del_clkout~8 signal_out~reg0 } "NODE_NAME" } } { "dpll.v" "" { Text "D:/so2007/cpld_pro/DPLL2007/DPLL0227+V+qt6/dpll.v" 145 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.251 ns ( 32.18 % ) " "Info: Total cell delay = 2.251 ns ( 32.18 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.743 ns ( 67.82 % ) " "Info: Total interconnect delay = 4.743 ns ( 67.82 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.994 ns" { clk cnt8[2] add_del_clkout~8 signal_out~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.994 ns" { clk clk~out0 cnt8[2] add_del_clkout~8 signal_out~reg0 } { 0.000ns 0.000ns 1.689ns 0.427ns 2.627ns } { 0.000ns 0.828ns 0.698ns 0.183ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "dpll.v" "" { Text "D:/so2007/cpld_pro/DPLL2007/DPLL0227+V+qt6/dpll.v" 145 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.653 ns + Longest register pin " "Info: + Longest register to pin delay is 4.653 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns signal_out~reg0 1 REG LC_X41_Y21_N9 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X41_Y21_N9; Fanout = 5; REG Node = 'signal_out~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { signal_out~reg0 } "NODE_NAME" } } { "dpll.v" "" { Text "D:/so2007/cpld_pro/DPLL2007/DPLL0227+V+qt6/dpll.v" 145 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.249 ns) + CELL(2.404 ns) 4.653 ns signal_out 2 PIN PIN_W8 0 " "Info: 2: + IC(2.249 ns) + CELL(2.404 ns) = 4.653 ns; Loc. = PIN_W8; Fanout = 0; PIN Node = 'signal_out'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.653 ns" { signal_out~reg0 signal_out } "NODE_NAME" } } { "dpll.v" "" { Text "D:/so2007/cpld_pro/DPLL2007/DPLL0227+V+qt6/dpll.v" 8 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.404 ns ( 51.67 % ) " "Info: Total cell delay = 2.404 ns ( 51.67 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.249 ns ( 48.33 % ) " "Info: Total interconnect delay = 2.249 ns ( 48.33 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.653 ns" { signal_out~reg0 signal_out } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.653 ns" { signal_out~reg0 signal_out } { 0.000ns 2.249ns } { 0.000ns 2.404ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.994 ns" { clk cnt8[2] add_del_clkout~8 signal_out~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.994 ns" { clk clk~out0 cnt8[2] add_del_clkout~8 signal_out~reg0 } { 0.000ns 0.000ns 1.689ns 0.427ns 2.627ns } { 0.000ns 0.828ns 0.698ns 0.183ns 0.542ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.653 ns" { signal_out~reg0 signal_out } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.653 ns" { signal_out~reg0 signal_out } { 0.000ns 2.249ns } { 0.000ns 2.404ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "dpout_delay signal_in clk -2.495 ns register " "Info: th for register \"dpout_delay\" (data pin = \"signal_in\", clock pin = \"clk\") is -2.495 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.893 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 2.893 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 32 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 32; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dpll.v" "" { Text "D:/so2007/cpld_pro/DPLL2007/DPLL0227+V+qt6/dpll.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.523 ns) + CELL(0.542 ns) 2.893 ns dpout_delay 2 REG LC_X41_Y21_N0 5 " "Info: 2: + IC(1.523 ns) + CELL(0.542 ns) = 2.893 ns; Loc. = LC_X41_Y21_N0; Fanout = 5; REG Node = 'dpout_delay'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.065 ns" { clk dpout_delay } "NODE_NAME" } } { "dpll.v" "" { Text "D:/so2007/cpld_pro/DPLL2007/DPLL0227+V+qt6/dpll.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 47.36 % ) " "Info: Total cell delay = 1.370 ns ( 47.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.523 ns ( 52.64 % ) " "Info: Total interconnect delay = 1.523 ns ( 52.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.893 ns" { clk dpout_delay } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.893 ns" { clk clk~out0 dpout_delay } { 0.000ns 0.000ns 1.523ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" {  } { { "dpll.v" "" { Text "D:/so2007/cpld_pro/DPLL2007/DPLL0227+V+qt6/dpll.v" 19 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.488 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.488 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.234 ns) 1.234 ns signal_in 1 PIN PIN_J2 3 " "Info: 1: + IC(0.000 ns) + CELL(1.234 ns) = 1.234 ns; Loc. = PIN_J2; Fanout = 3; PIN Node = 'signal_in'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { signal_in } "NODE_NAME" } } { "dpll.v" "" { Text "D:/so2007/cpld_pro/DPLL2007/DPLL0227+V+qt6/dpll.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.796 ns) + CELL(0.458 ns) 5.488 ns dpout_delay 2 REG LC_X41_Y21_N0 5 " "Info: 2: + IC(3.796 ns) + CELL(0.458 ns) = 5.488 ns; Loc. = LC_X41_Y21_N0; Fanout = 5; REG Node = 'dpout_delay'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.254 ns" { signal_in dpout_delay } "NODE_NAME" } } { "dpll.v" "" { Text "D:/so2007/cpld_pro/DPLL2007/DPLL0227+V+qt6/dpll.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.692 ns ( 30.83 % ) " "Info: Total cell delay = 1.692 ns ( 30.83 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.796 ns ( 69.17 % ) " "Info: Total interconnect delay = 3.796 ns ( 69.17 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.488 ns" { signal_in dpout_delay } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.488 ns" { signal_in signal_in~out0 dpout_delay } { 0.000ns 0.000ns 3.796ns } { 0.000ns 1.234ns 0.458ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.893 ns" { clk dpout_delay } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.893 ns" { clk clk~out0 dpout_delay } { 0.000ns 0.000ns 1.523ns } { 0.000ns 0.828ns 0.542ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.488 ns" { signal_in dpout_delay } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.488 ns" { signal_in signal_in~out0 dpout_delay } { 0.000ns 0.000ns 3.796ns } { 0.000ns 1.234ns 0.458ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Mar 20 22:12:56 2007 " "Info: Processing ended: Tue Mar 20 22:12:56 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}