dpll.tan.qmsg

用一片CPLD实现数字锁相环,用VHDL或V语言.

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "cnt8\[2\] " "Info: Detected ripple clock \"cnt8\[2\]\" as buffer" {  } { { "dpll.v" "" { Text "D:/so2007/cpld_pro/DPLL2007/DPLL0227+V+qt6/dpll.v" 111 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "cnt8\[2\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_GATED_CLK" "add_del_clkout~8 " "Info: Detected gated clock \"add_del_clkout~8\" as buffer" {  } { { "dpll.v" "" { Text "D:/so2007/cpld_pro/DPLL2007/DPLL0227+V+qt6/dpll.v" 14 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "add_del_clkout~8" } } } }  } 0 0 "Detected gated clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "reset register cnt_N\[0\] register signal_out~reg0 369.41 MHz 2.707 ns Internal " "Info: Clock \"reset\" has Internal fmax of 369.41 MHz between source register \"cnt_N\[0\]\" and destination register \"signal_out~reg0\" (period= 2.707 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.519 ns + Longest register register " "Info: + Longest register to register delay is 2.519 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt_N\[0\] 1 REG LC_X33_Y20_N8 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X33_Y20_N8; Fanout = 4; REG Node = 'cnt_N\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { cnt_N[0] } "NODE_NAME" } } { "dpll.v" "" { Text "D:/so2007/cpld_pro/DPLL2007/DPLL0227+V+qt6/dpll.v" 145 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.406 ns) + CELL(0.366 ns) 0.772 ns Equal6~114 2 COMB LC_X33_Y20_N5 2 " "Info: 2: + IC(0.406 ns) + CELL(0.366 ns) = 0.772 ns; Loc. = LC_X33_Y20_N5; Fanout = 2; COMB Node = 'Equal6~114'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.772 ns" { cnt_N[0] Equal6~114 } "NODE_NAME" } } { "dpll.v" "" { Text "D:/so2007/cpld_pro/DPLL2007/DPLL0227+V+qt6/dpll.v" 152 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.524 ns) + CELL(0.223 ns) 2.519 ns signal_out~reg0 3 REG LC_X41_Y21_N9 5 " "Info: 3: + IC(1.524 ns) + CELL(0.223 ns) = 2.519 ns; Loc. = LC_X41_Y21_N9; Fanout = 5; REG Node = 'signal_out~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.747 ns" { Equal6~114 signal_out~reg0 } "NODE_NAME" } } { "dpll.v" "" { Text "D:/so2007/cpld_pro/DPLL2007/DPLL0227+V+qt6/dpll.v" 145 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.589 ns ( 23.38 % ) " "Info: Total cell delay = 0.589 ns ( 23.38 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.930 ns ( 76.62 % ) " "Info: Total interconnect delay = 1.930 ns ( 76.62 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.519 ns" { cnt_N[0] Equal6~114 signal_out~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.519 ns" { cnt_N[0] Equal6~114 signal_out~reg0 } { 0.000ns 0.406ns 1.524ns } { 0.000ns 0.366ns 0.223ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.022 ns - Smallest " "Info: - Smallest clock skew is -0.022 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "reset destination 5.131 ns + Shortest register " "Info: + Shortest clock path from clock \"reset\" to destination register is 5.131 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns reset 1 CLK PIN_M21 43 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_M21; Fanout = 43; CLK Node = 'reset'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "dpll.v" "" { Text "D:/so2007/cpld_pro/DPLL2007/DPLL0227+V+qt6/dpll.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.162 ns) + CELL(0.075 ns) 1.962 ns add_del_clkout~8 2 COMB LC_X1_Y17_N8 10 " "Info: 2: + IC(1.162 ns) + CELL(0.075 ns) = 1.962 ns; Loc. = LC_X1_Y17_N8; Fanout = 10; COMB Node = 'add_del_clkout~8'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.237 ns" { reset add_del_clkout~8 } "NODE_NAME" } } { "dpll.v" "" { Text "D:/so2007/cpld_pro/DPLL2007/DPLL0227+V+qt6/dpll.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.627 ns) + CELL(0.542 ns) 5.131 ns signal_out~reg0 3 REG LC_X41_Y21_N9 5 " "Info: 3: + IC(2.627 ns) + CELL(0.542 ns) = 5.131 ns; Loc. = LC_X41_Y21_N9; Fanout = 5; REG Node = 'signal_out~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.169 ns" { add_del_clkout~8 signal_out~reg0 } "NODE_NAME" } } { "dpll.v" "" { Text "D:/so2007/cpld_pro/DPLL2007/DPLL0227+V+qt6/dpll.v" 145 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.342 ns ( 26.15 % ) " "Info: Total cell delay = 1.342 ns ( 26.15 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.789 ns ( 73.85 % ) " "Info: Total interconnect delay = 3.789 ns ( 73.85 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.131 ns" { reset add_del_clkout~8 signal_out~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.131 ns" { reset reset~out0 add_del_clkout~8 signal_out~reg0 } { 0.000ns 0.000ns 1.162ns 2.627ns } { 0.000ns 0.725ns 0.075ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "reset source 5.153 ns - Longest register " "Info: - Longest clock path from clock \"reset\" to source register is 5.153 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns reset 1 CLK PIN_M21 43 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_M21; Fanout = 43; CLK Node = 'reset'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "dpll.v" "" { Text "D:/so2007/cpld_pro/DPLL2007/DPLL0227+V+qt6/dpll.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.162 ns) + CELL(0.075 ns) 1.962 ns add_del_clkout~8 2 COMB LC_X1_Y17_N8 10 " "Info: 2: + IC(1.162 ns) + CELL(0.075 ns) = 1.962 ns; Loc. = LC_X1_Y17_N8; Fanout = 10; COMB Node = 'add_del_clkout~8'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.237 ns" { reset add_del_clkout~8 } "NODE_NAME" } } { "dpll.v" "" { Text "D:/so2007/cpld_pro/DPLL2007/DPLL0227+V+qt6/dpll.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.649 ns) + CELL(0.542 ns) 5.153 ns cnt_N\[0\] 3 REG LC_X33_Y20_N8 4 " "Info: 3: + IC(2.649 ns) + CELL(0.542 ns) = 5.153 ns; Loc. = LC_X33_Y20_N8; Fanout = 4; REG Node = 'cnt_N\[0\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.191 ns" { add_del_clkout~8 cnt_N[0] } "NODE_NAME" } } { "dpll.v" "" { Text "D:/so2007/cpld_pro/DPLL2007/DPLL0227+V+qt6/dpll.v" 145 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.342 ns ( 26.04 % ) " "Info: Total cell delay = 1.342 ns ( 26.04 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.811 ns ( 73.96 % ) " "Info: Total interconnect delay = 3.811 ns ( 73.96 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.153 ns" { reset add_del_clkout~8 cnt_N[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.153 ns" { reset reset~out0 add_del_clkout~8 cnt_N[0] } { 0.000ns 0.000ns 1.162ns 2.649ns } { 0.000ns 0.725ns 0.075ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.131 ns" { reset add_del_clkout~8 signal_out~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.131 ns" { reset reset~out0 add_del_clkout~8 signal_out~reg0 } { 0.000ns 0.000ns 1.162ns 2.627ns } { 0.000ns 0.725ns 0.075ns 0.542ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.153 ns" { reset add_del_clkout~8 cnt_N[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.153 ns" { reset reset~out0 add_del_clkout~8 cnt_N[0] } { 0.000ns 0.000ns 1.162ns 2.649ns } { 0.000ns 0.725ns 0.075ns 0.542ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "dpll.v" "" { Text "D:/so2007/cpld_pro/DPLL2007/DPLL0227+V+qt6/dpll.v" 145 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "dpll.v" "" { Text "D:/so2007/cpld_pro/DPLL2007/DPLL0227+V+qt6/dpll.v" 145 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.519 ns" { cnt_N[0] Equal6~114 signal_out~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.519 ns" { cnt_N[0] Equal6~114 signal_out~reg0 } { 0.000ns 0.406ns 1.524ns } { 0.000ns 0.366ns 0.223ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.131 ns" { reset add_del_clkout~8 signal_out~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.131 ns" { reset reset~out0 add_del_clkout~8 signal_out~reg0 } { 0.000ns 0.000ns 1.162ns 2.627ns } { 0.000ns 0.725ns 0.075ns 0.542ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.153 ns" { reset add_del_clkout~8 cnt_N[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.153 ns" { reset reset~out0 add_del_clkout~8 cnt_N[0] } { 0.000ns 0.000ns 1.162ns 2.649ns } { 0.000ns 0.725ns 0.075ns 0.542ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register signal_out~reg0 register delclk 138.48 MHz 7.221 ns Internal " "Info: Clock \"clk\" has Internal fmax of 138.48 MHz between source register \"signal_out~reg0\" and destination register \"delclk\" (period= 7.221 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.120 ns + Longest register register " "Info: + Longest register to register delay is 3.120 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns signal_out~reg0 1 REG LC_X41_Y21_N9 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X41_Y21_N9; Fanout = 5; REG Node = 'signal_out~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { signal_out~reg0 } "NODE_NAME" } } { "dpll.v" "" { Text "D:/so2007/cpld_pro/DPLL2007/DPLL0227+V+qt6/dpll.v" 145 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.396 ns) + CELL(0.075 ns) 0.471 ns dpout~1 2 COMB LC_X41_Y21_N0 42 " "Info: 2: + IC(0.396 ns) + CELL(0.075 ns) = 0.471 ns; Loc. = LC_X41_Y21_N0; Fanout = 42; COMB Node = 'dpout~1'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.471 ns" { signal_out~reg0 dpout~1 } "NODE_NAME" } } { "dpll.v" "" { Text "D:/so2007/cpld_pro/DPLL2007/DPLL0227+V+qt6/dpll.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.330 ns) + CELL(0.319 ns) 3.120 ns delclk 3 REG LC_X1_Y17_N4 2 " "Info: 3: + IC(2.330 ns) + CELL(0.319 ns) = 3.120 ns; Loc. = LC_X1_Y17_N4; Fanout = 2; REG Node = 'delclk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.649 ns" { dpout~1 delclk } "NODE_NAME" } } { "dpll.v" "" { Text "D:/so2007/cpld_pro/DPLL2007/DPLL0227+V+qt6/dpll.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.394 ns ( 12.63 % ) " "Info: Total cell delay = 0.394 ns ( 12.63 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.726 ns ( 87.37 % ) " "Info: Total interconnect delay = 2.726 ns ( 87.37 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.120 ns" { signal_out~reg0 dpout~1 delclk } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.120 ns" { signal_out~reg0 dpout~1 delclk } { 0.000ns 0.396ns 2.330ns } { 0.000ns 0.075ns 0.319ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-3.935 ns - Smallest " "Info: - Smallest clock skew is -3.935 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.059 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.059 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 32 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 32; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dpll.v" "" { Text "D:/so2007/cpld_pro/DPLL2007/DPLL0227+V+qt6/dpll.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.689 ns) + CELL(0.542 ns) 3.059 ns delclk 2 REG LC_X1_Y17_N4 2 " "Info: 2: + IC(1.689 ns) + CELL(0.542 ns) = 3.059 ns; Loc. = LC_X1_Y17_N4; Fanout = 2; REG Node = 'delclk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.231 ns" { clk delclk } "NODE_NAME" } } { "dpll.v" "" { Text "D:/so2007/cpld_pro/DPLL2007/DPLL0227+V+qt6/dpll.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 44.79 % ) " "Info: Total cell delay = 1.370 ns ( 44.79 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.689 ns ( 55.21 % ) " "Info: Total interconnect delay = 1.689 ns ( 55.21 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.059 ns" { clk delclk } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.059 ns" { clk clk~out0 delclk } { 0.000ns 0.000ns 1.689ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 6.994 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 6.994 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 32 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 32; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dpll.v" "" { Text "D:/so2007/cpld_pro/DPLL2007/DPLL0227+V+qt6/dpll.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.689 ns) + CELL(0.698 ns) 3.215 ns cnt8\[2\] 2 REG LC_X1_Y17_N5 4 " "Info: 2: + IC(1.689 ns) + CELL(0.698 ns) = 3.215 ns; Loc. = LC_X1_Y17_N5; Fanout = 4; REG Node = 'cnt8\[2\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.387 ns" { clk cnt8[2] } "NODE_NAME" } } { "dpll.v" "" { Text "D:/so2007/cpld_pro/DPLL2007/DPLL0227+V+qt6/dpll.v" 111 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.427 ns) + CELL(0.183 ns) 3.825 ns add_del_clkout~8 3 COMB LC_X1_Y17_N8 10 " "Info: 3: + IC(0.427 ns) + CELL(0.183 ns) = 3.825 ns; Loc. = LC_X1_Y17_N8; Fanout = 10; COMB Node = 'add_del_clkout~8'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.610 ns" { cnt8[2] add_del_clkout~8 } "NODE_NAME" } } { "dpll.v" "" { Text "D:/so2007/cpld_pro/DPLL2007/DPLL0227+V+qt6/dpll.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.627 ns) + CELL(0.542 ns) 6.994 ns signal_out~reg0 4 REG LC_X41_Y21_N9 5 " "Info: 4: + IC(2.627 ns) + CELL(0.542 ns) = 6.994 ns; Loc. = LC_X41_Y21_N9; Fanout = 5; REG Node = 'signal_out~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.169 ns" { add_del_clkout~8 signal_out~reg0 } "NODE_NAME" } } { "dpll.v" "" { Text "D:/so2007/cpld_pro/DPLL2007/DPLL0227+V+qt6/dpll.v" 145 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.251 ns ( 32.18 % ) " "Info: Total cell delay = 2.251 ns ( 32.18 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.743 ns ( 67.82 % ) " "Info: Total interconnect delay = 4.743 ns ( 67.82 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.994 ns" { clk cnt8[2] add_del_clkout~8 signal_out~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.994 ns" { clk clk~out0 cnt8[2] add_del_clkout~8 signal_out~reg0 } { 0.000ns 0.000ns 1.689ns 0.427ns 2.627ns } { 0.000ns 0.828ns 0.698ns 0.183ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.059 ns" { clk delclk } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.059 ns" { clk clk~out0 delclk } { 0.000ns 0.000ns 1.689ns } { 0.000ns 0.828ns 0.542ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.994 ns" { clk cnt8[2] add_del_clkout~8 signal_out~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.994 ns" { clk clk~out0 cnt8[2] add_del_clkout~8 signal_out~reg0 } { 0.000ns 0.000ns 1.689ns 0.427ns 2.627ns } { 0.000ns 0.828ns 0.698ns 0.183ns 0.542ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "dpll.v" "" { Text "D:/so2007/cpld_pro/DPLL2007/DPLL0227+V+qt6/dpll.v" 145 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "dpll.v" "" { Text "D:/so2007/cpld_pro/DPLL2007/DPLL0227+V+qt6/dpll.v" 12 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.120 ns" { signal_out~reg0 dpout~1 delclk } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.120 ns" { signal_out~reg0 dpout~1 delclk } { 0.000ns 0.396ns 2.330ns } { 0.000ns 0.075ns 0.319ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.059 ns" { clk delclk } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.059 ns" { clk clk~out0 delclk } { 0.000ns 0.000ns 1.689ns } { 0.000ns 0.828ns 0.542ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.994 ns" { clk cnt8[2] add_del_clkout~8 signal_out~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.994 ns" { clk clk~out0 cnt8[2] add_del_clkout~8 signal_out~reg0 } { 0.000ns 0.000ns 1.689ns 0.427ns 2.627ns } { 0.000ns 0.828ns 0.698ns 0.183ns 0.542ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "delclk signal_in clk 4.910 ns register " "Info: tsu for register \"delclk\" (data pin = \"signal_in\", clock pin = \"clk\") is 4.910 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.959 ns + Longest pin register " "Info: + Longest pin to register delay is 7.959 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.234 ns) 1.234 ns signal_in 1 PIN PIN_J2 3 " "Info: 1: + IC(0.000 ns) + CELL(1.234 ns) = 1.234 ns; Loc. = PIN_J2; Fanout = 3; PIN Node = 'signal_in'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { signal_in } "NODE_NAME" } } { "dpll.v" "" { Text "D:/so2007/cpld_pro/DPLL2007/DPLL0227+V+qt6/dpll.v" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.796 ns) + CELL(0.280 ns) 5.310 ns dpout~1 2 COMB LC_X41_Y21_N0 42 " "Info: 2: + IC(3.796 ns) + CELL(0.280 ns) = 5.310 ns; Loc. = LC_X41_Y21_N0; Fanout = 42; COMB Node = 'dpout~1'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.076 ns" { signal_in dpout~1 } "NODE_NAME" } } { "dpll.v" "" { Text "D:/so2007/cpld_pro/DPLL2007/DPLL0227+V+qt6/dpll.v" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.330 ns) + CELL(0.319 ns) 7.959 ns delclk 3 REG LC_X1_Y17_N4 2 " "Info: 3: + IC(2.330 ns) + CELL(0.319 ns) = 7.959 ns; Loc. = LC_X1_Y17_N4; Fanout = 2; REG Node = 'delclk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.649 ns" { dpout~1 delclk } "NODE_NAME" } } { "dpll.v" "" { Text "D:/so2007/cpld_pro/DPLL2007/DPLL0227+V+qt6/dpll.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.833 ns ( 23.03 % ) " "Info: Total cell delay = 1.833 ns ( 23.03 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.126 ns ( 76.97 % ) " "Info: Total interconnect delay = 6.126 ns ( 76.97 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.959 ns" { signal_in dpout~1 delclk } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.959 ns" { signal_in signal_in~out0 dpout~1 delclk } { 0.000ns 0.000ns 3.796ns 2.330ns } { 0.000ns 1.234ns 0.280ns 0.319ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "dpll.v" "" { Text "D:/so2007/cpld_pro/DPLL2007/DPLL0227+V+qt6/dpll.v" 12 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.059 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 3.059 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns clk 1 CLK PIN_M20 32 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 32; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "dpll.v" "" { Text "D:/so2007/cpld_pro/DPLL2007/DPLL0227+V+qt6/dpll.v" 6 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.689 ns) + CELL(0.542 ns) 3.059 ns delclk 2 REG LC_X1_Y17_N4 2 " "Info: 2: + IC(1.689 ns) + CELL(0.542 ns) = 3.059 ns; Loc. = LC_X1_Y17_N4; Fanout = 2; REG Node = 'delclk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.231 ns" { clk delclk } "NODE_NAME" } } { "dpll.v" "" { Text "D:/so2007/cpld_pro/DPLL2007/DPLL0227+V+qt6/dpll.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 44.79 % ) " "Info: Total cell delay = 1.370 ns ( 44.79 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.689 ns ( 55.21 % ) " "Info: Total interconnect delay = 1.689 ns ( 55.21 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.059 ns" { clk delclk } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.059 ns" { clk clk~out0 delclk } { 0.000ns 0.000ns 1.689ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.959 ns" { signal_in dpout~1 delclk } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.959 ns" { signal_in signal_in~out0 dpout~1 delclk } { 0.000ns 0.000ns 3.796ns 2.330ns } { 0.000ns 1.234ns 0.280ns 0.319ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.059 ns" { clk delclk } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.059 ns" { clk clk~out0 delclk } { 0.000ns 0.000ns 1.689ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}