dpll.flow.rpt

用一片CPLD实现数字锁相环,用VHDL或V语言.

Flow report for dpll
Tue Mar 20 22:12:56 2007
Version 6.0 Build 178 04/27/2006 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Flow Summary
  3. Flow Settings
  4. Flow Non-Default Global Settings
  5. Flow Elapsed Time
  6. Flow Log



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+---------------------------------------------------------------------+
; Flow Summary                                                        ;
+--------------------------+------------------------------------------+
; Flow Status              ; Successful - Tue Mar 20 22:12:56 2007    ;
; Quartus II Version       ; 6.0 Build 178 04/27/2006 SJ Full Version ;
; Revision Name            ; dpll                                     ;
; Top-level Entity Name    ; dpll                                     ;
; Family                   ; Stratix                                  ;
; Met timing requirements  ; Yes                                      ;
; Total logic elements     ; 92 / 10,570 ( < 1 % )                    ;
; Total pins               ; 5 / 336 ( 1 % )                          ;
; Total virtual pins       ; 0                                        ;
; Total memory bits        ; 0 / 920,448 ( 0 % )                      ;
; DSP block 9-bit elements ; 0 / 48 ( 0 % )                           ;
; Total PLLs               ; 0 / 6 ( 0 % )                            ;
; Total DLLs               ; 0 / 2 ( 0 % )                            ;
; Device                   ; EP1S10F484C5                             ;
; Timing Models            ; Final                                    ;
+--------------------------+------------------------------------------+


+-----------------------------------------+
; Flow Settings                           ;
+-------------------+---------------------+
; Option            ; Setting             ;
+-------------------+---------------------+
; Start date & time ; 03/20/2007 22:11:12 ;
; Main task         ; Compilation         ;
; Revision Name     ; dpll                ;
+-------------------+---------------------+


+--------------------------------------------------------------------+
; Flow Non-Default Global Settings                                   ;
+-----------------+-------+---------------+-------------+------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+-----------------+-------+---------------+-------------+------------+


+-------------------------------------+
; Flow Elapsed Time                   ;
+----------------------+--------------+
; Module Name          ; Elapsed Time ;
+----------------------+--------------+
; Analysis & Synthesis ; 00:00:37     ;
; Fitter               ; 00:00:43     ;
; Assembler            ; 00:00:13     ;
; Timing Analyzer      ; 00:00:02     ;
; Total                ; 00:01:35     ;
+----------------------+--------------+


------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off dpll -c dpll
quartus_fit --read_settings_files=off --write_settings_files=off dpll -c dpll
quartus_asm --read_settings_files=off --write_settings_files=off dpll -c dpll
quartus_tan --read_settings_files=off --write_settings_files=off dpll -c dpll --timing_analysis_only