dpll.fit.summary

来自「用一片CPLD实现数字锁相环,用VHDL或V语言.」· SUMMARY 代码 · 共 15 行

Fitter Status : Successful - Tue Mar 20 22:12:33 2007
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version
Revision Name : dpll
Top-level Entity Name : dpll
Family : Stratix
Device : EP1S10F484C5
Timing Models : Final
Total logic elements : 92 / 10,570 ( < 1 % )
Total pins : 5 / 336 ( 1 % )
Total virtual pins : 0
Total memory bits : 0 / 920,448 ( 0 % )
DSP block 9-bit elements : 0 / 48 ( 0 % )
Total PLLs : 0 / 6 ( 0 % )
Total DLLs : 0 / 2 ( 0 % )