div20pll.map.qmsg

用一片CPLD实现数字锁相环,用VHDL或V语言.

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Feb 27 10:45:37 2007 " "Info: Processing started: Tue Feb 27 10:45:37 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off Div20PLL -c Div20PLL " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Div20PLL -c Div20PLL" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Div20PLL.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file Div20PLL.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 Div20PLL-myFavor " "Info: Found design unit 1: Div20PLL-myFavor" {  } { { "Div20PLL.vhd" "" { Text "D:/so2006/cpld-pro/数字环/DPLL0226/Div20PLL.vhd" 17 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 Div20PLL " "Info: Found entity 1: Div20PLL" {  } { { "Div20PLL.vhd" "" { Text "D:/so2006/cpld-pro/数字环/DPLL0226/Div20PLL.vhd" 10 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "Div20PLL " "Info: Elaborating entity \"Div20PLL\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_NET" "losreg\[1\] X Div20PLL.vhd(41) " "Warning (10030): Tied undriven net \"losreg\[1\]\" at Div20PLL.vhd(41) to X" {  } { { "Div20PLL.vhd" "" { Text "D:/so2006/cpld-pro/数字环/DPLL0226/Div20PLL.vhd" 41 0 0 } }  } 0 10030 "Tied undriven net \"%1!s!\" at %3!s! to %2!s!" 0 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_NET" "losreg\[0\] X Div20PLL.vhd(41) " "Warning (10030): Tied undriven net \"losreg\[0\]\" at Div20PLL.vhd(41) to X" {  } { { "Div20PLL.vhd" "" { Text "D:/so2006/cpld-pro/数字环/DPLL0226/Div20PLL.vhd" 41 0 0 } }  } 0 10030 "Tied undriven net \"%1!s!\" at %3!s! to %2!s!" 0 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_NET" "leadreg\[1\] X Div20PLL.vhd(41) " "Warning (10030): Tied undriven net \"leadreg\[1\]\" at Div20PLL.vhd(41) to X" {  } { { "Div20PLL.vhd" "" { Text "D:/so2006/cpld-pro/数字环/DPLL0226/Div20PLL.vhd" 41 0 0 } }  } 0 10030 "Tied undriven net \"%1!s!\" at %3!s! to %2!s!" 0 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_NET" "leadreg\[0\] X Div20PLL.vhd(41) " "Warning (10030): Tied undriven net \"leadreg\[0\]\" at Div20PLL.vhd(41) to X" {  } { { "Div20PLL.vhd" "" { Text "D:/so2006/cpld-pro/数字环/DPLL0226/Div20PLL.vhd" 41 0 0 } }  } 0 10030 "Tied undriven net \"%1!s!\" at %3!s! to %2!s!" 0 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_NET" "lagreg\[1\] X Div20PLL.vhd(41) " "Warning (10030): Tied undriven net \"lagreg\[1\]\" at Div20PLL.vhd(41) to X" {  } { { "Div20PLL.vhd" "" { Text "D:/so2006/cpld-pro/数字环/DPLL0226/Div20PLL.vhd" 41 0 0 } }  } 0 10030 "Tied undriven net \"%1!s!\" at %3!s! to %2!s!" 0 0}
{ "Warning" "WVRFX_VRFC_DRIVERLESS_NET" "lagreg\[0\] X Div20PLL.vhd(41) " "Warning (10030): Tied undriven net \"lagreg\[0\]\" at Div20PLL.vhd(41) to X" {  } { { "Div20PLL.vhd" "" { Text "D:/so2006/cpld-pro/数字环/DPLL0226/Div20PLL.vhd" 41 0 0 } }  } 0 10030 "Tied undriven net \"%1!s!\" at %3!s! to %2!s!" 0 0}
{ "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN_HDR" "1 " "Warning: Design contains 1 input pin(s) that do not drive logic" { { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "flow " "Warning: No output dependent on input pin \"flow\"" {  } { { "Div20PLL.vhd" "" { Text "D:/so2006/cpld-pro/数字环/DPLL0226/Div20PLL.vhd" 12 -1 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0}  } {  } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "11 " "Info: Implemented 11 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "1 " "Info: Implemented 1 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "8 " "Info: Implemented 8 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 8 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 8 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Tue Feb 27 10:45:38 2007 " "Info: Processing ended: Tue Feb 27 10:45:38 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}