div20pll.map.rpt

用一片CPLD实现数字锁相环,用VHDL或V语言.

; PowerPlay Power Optimization                                       ; Normal compilation ; Normal compilation ;
; HDL message level                                                  ; Level2             ; Level2             ;
+--------------------------------------------------------------------+--------------------+--------------------+


+------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                 ;
+----------------------------------+-----------------+-----------------+-------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type       ; File Name with Absolute Path                    ;
+----------------------------------+-----------------+-----------------+-------------------------------------------------+
; Div20PLL.vhd                     ; yes             ; User VHDL File  ; D:/so2006/cpld-pro/数字环/DPLL0226/Div20PLL.vhd ;
+----------------------------------+-----------------+-----------------+-------------------------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Total logic elements                        ; 8     ;
;     -- Combinational with no register       ; 1     ;
;     -- Register only                        ; 2     ;
;     -- Combinational with a register        ; 5     ;
;                                             ;       ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 3     ;
;     -- 3 input functions                    ; 2     ;
;     -- 2 input functions                    ; 0     ;
;     -- 1 input functions                    ; 1     ;
;     -- 0 input functions                    ; 0     ;
;         -- Combinational cells for routing  ; 0     ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 8     ;
;     -- arithmetic mode                      ; 0     ;
;     -- qfbk mode                            ; 0     ;
;     -- register cascade mode                ; 0     ;
;     -- synchronous clear/load mode          ; 0     ;
;     -- asynchronous clear/load mode         ; 0     ;
;                                             ;       ;
; Total registers                             ; 7     ;
; I/O pins                                    ; 3     ;
; Maximum fan-out node                        ; clock ;
; Maximum fan-out                             ; 7     ;
; Total fan-out                               ; 29    ;
; Average fan-out                             ; 2.64  ;
+---------------------------------------------+-------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                             ;
+----------------------------+-------------+--------------+-------------+-------+------+--------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; M512s ; M4Ks ; M-RAMs ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+-------+------+--------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; |Div20PLL                  ; 8 (8)       ; 7            ; 0           ; 0     ; 0    ; 0      ; 0            ; 0       ; 0         ; 0         ; 3    ; 0            ; 1 (1)        ; 2 (2)             ; 5 (5)            ; 0 (0)           ; 0 (0)      ; |Div20PLL           ;
+----------------------------+-------------+--------------+-------------+-------+------+--------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 7     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 3:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; Yes        ; |Div20PLL|phase[0]         ;
; 4:1                ; 5 bits    ; 10 LEs        ; 10 LEs               ; 0 LEs                  ; Yes        ; |Div20PLL|reg[3]           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Tue Feb 27 10:45:37 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Div20PLL -c Div20PLL
Info: Found 2 design units, including 1 entities, in source file Div20PLL.vhd
    Info: Found design unit 1: Div20PLL-myFavor
    Info: Found entity 1: Div20PLL
Info: Elaborating entity "Div20PLL" for the top level hierarchy
Warning (10030): Tied undriven net "losreg[1]" at Div20PLL.vhd(41) to X
Warning (10030): Tied undriven net "losreg[0]" at Div20PLL.vhd(41) to X
Warning (10030): Tied undriven net "leadreg[1]" at Div20PLL.vhd(41) to X
Warning (10030): Tied undriven net "leadreg[0]" at Div20PLL.vhd(41) to X
Warning (10030): Tied undriven net "lagreg[1]" at Div20PLL.vhd(41) to X
Warning (10030): Tied undriven net "lagreg[0]" at Div20PLL.vhd(41) to X
Warning: Design contains 1 input pin(s) that do not drive logic
    Warning: No output dependent on input pin "flow"
Info: Implemented 11 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 1 output pins
    Info: Implemented 8 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 8 warnings
    Info: Processing ended: Tue Feb 27 10:45:38 2007
    Info: Elapsed time: 00:00:02