div20pll.map.summary

用一片CPLD实现数字锁相环,用VHDL或V语言.

Analysis & Synthesis Status : Successful - Tue Feb 27 10:45:38 2007
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version
Revision Name : Div20PLL
Top-level Entity Name : Div20PLL
Family : Stratix
Total logic elements : 8
Total pins : 3
Total virtual pins : 0
Total memory bits : 0
DSP block 9-bit elements : 0
Total PLLs : 0
Total DLLs : 0