div20pll.tan.rpt

用一片CPLD实现数字锁相环,用VHDL或V语言.

+-------+------------------------------------------------+---------+---------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period)                           ; From    ; To      ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+---------+---------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; reg[2]  ; clk4M   ; clock      ; clock    ; None                        ; None                      ; 1.150 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; reg[0]  ; reg[3]  ; clock      ; clock    ; None                        ; None                      ; 0.989 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; reg[1]  ; reg[2]  ; clock      ; clock    ; None                        ; None                      ; 0.969 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; reg[1]  ; clk4M   ; clock      ; clock    ; None                        ; None                      ; 0.956 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; dly3reg ; clk4M   ; clock      ; clock    ; None                        ; None                      ; 0.931 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; reg[1]  ; reg[0]  ; clock      ; clock    ; None                        ; None                      ; 0.867 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; reg[2]  ; reg[3]  ; clock      ; clock    ; None                        ; None                      ; 0.866 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; reg[1]  ; reg[3]  ; clock      ; clock    ; None                        ; None                      ; 0.865 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; reg[2]  ; reg[1]  ; clock      ; clock    ; None                        ; None                      ; 0.865 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; reg[1]  ; reg[1]  ; clock      ; clock    ; None                        ; None                      ; 0.864 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; reg[3]  ; reg[2]  ; clock      ; clock    ; None                        ; None                      ; 0.862 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; reg[3]  ; clk4M   ; clock      ; clock    ; None                        ; None                      ; 0.859 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; reg[2]  ; reg[2]  ; clock      ; clock    ; None                        ; None                      ; 0.852 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; clk4M   ; clk4M   ; clock      ; clock    ; None                        ; None                      ; 0.717 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; reg[0]  ; clk4M   ; clock      ; clock    ; None                        ; None                      ; 0.694 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; reg[0]  ; reg[1]  ; clock      ; clock    ; None                        ; None                      ; 0.659 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; reg[0]  ; reg[2]  ; clock      ; clock    ; None                        ; None                      ; 0.658 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; reg[0]  ; reg[4]  ; clock      ; clock    ; None                        ; None                      ; 0.657 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; reg[4]  ; reg[3]  ; clock      ; clock    ; None                        ; None                      ; 0.639 ns                ;
; N/A   ; Restricted to 422.12 MHz ( period = 2.369 ns ) ; reg[3]  ; dly3reg ; clock      ; clock    ; None                        ; None                      ; 0.616 ns                ;
+-------+------------------------------------------------+---------+---------+------------+----------+-----------------------------+---------------------------+-------------------------+


+-----------------------------------------------------------------+
; tco                                                             ;
+-------+--------------+------------+-------+--------+------------+
; Slack ; Required tco ; Actual tco ; From  ; To     ; From Clock ;
+-------+--------------+------------+-------+--------+------------+
; N/A   ; None         ; 6.927 ns   ; clk4M ; clkout ; clock      ;
+-------+--------------+------------+-------+--------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Tue Feb 27 10:45:53 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off Div20PLL -c Div20PLL --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clock" is an undefined clock
Info: Clock "clock" Internal fmax is restricted to 422.12 MHz between source register "reg[2]" and destination register "clk4M"
    Info: fmax restricted to clock pin edge rate 2.369 ns. Expand message to see actual delay path.
        Info: + Longest register to register delay is 1.150 ns
            Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X25_Y30_N9; Fanout = 4; REG Node = 'reg[2]'
            Info: 2: + IC(0.406 ns) + CELL(0.280 ns) = 0.686 ns; Loc. = LC_X25_Y30_N4; Fanout = 1; COMB Node = 'rst~29'
            Info: 3: + IC(0.241 ns) + CELL(0.223 ns) = 1.150 ns; Loc. = LC_X25_Y30_N5; Fanout = 2; REG Node = 'clk4M'
            Info: Total cell delay = 0.503 ns ( 43.74 % )
            Info: Total interconnect delay = 0.647 ns ( 56.26 % )
        Info: - Smallest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "clock" to destination register is 2.923 ns
                Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 7; CLK Node = 'clock'
                Info: 2: + IC(1.553 ns) + CELL(0.542 ns) = 2.923 ns; Loc. = LC_X25_Y30_N5; Fanout = 2; REG Node = 'clk4M'
                Info: Total cell delay = 1.370 ns ( 46.87 % )
                Info: Total interconnect delay = 1.553 ns ( 53.13 % )
            Info: - Longest clock path from clock "clock" to source register is 2.923 ns
                Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 7; CLK Node = 'clock'
                Info: 2: + IC(1.553 ns) + CELL(0.542 ns) = 2.923 ns; Loc. = LC_X25_Y30_N9; Fanout = 4; REG Node = 'reg[2]'
                Info: Total cell delay = 1.370 ns ( 46.87 % )
                Info: Total interconnect delay = 1.553 ns ( 53.13 % )
        Info: + Micro clock to output delay of source is 0.156 ns
        Info: + Micro setup delay of destination is 0.010 ns
Info: tco from clock "clock" to destination pin "clkout" through register "clk4M" is 6.927 ns
    Info: + Longest clock path from clock "clock" to source register is 2.923 ns
        Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_M20; Fanout = 7; CLK Node = 'clock'
        Info: 2: + IC(1.553 ns) + CELL(0.542 ns) = 2.923 ns; Loc. = LC_X25_Y30_N5; Fanout = 2; REG Node = 'clk4M'
        Info: Total cell delay = 1.370 ns ( 46.87 % )
        Info: Total interconnect delay = 1.553 ns ( 53.13 % )
    Info: + Micro clock to output delay of source is 0.156 ns
    Info: + Longest register to pin delay is 3.848 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X25_Y30_N5; Fanout = 2; REG Node = 'clk4M'
        Info: 2: + IC(1.161 ns) + CELL(2.687 ns) = 3.848 ns; Loc. = PIN_B13; Fanout = 0; PIN Node = 'clkout'
        Info: Total cell delay = 2.687 ns ( 69.83 % )
        Info: Total interconnect delay = 1.161 ns ( 30.17 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Tue Feb 27 10:45:53 2007
    Info: Elapsed time: 00:00:00