freedes.vhd.txt

HDL实现的DES算法

  ROUND01:  des_round port map (clk, reset, stall, encrypt,         encrypt_shift1,  decrypt_shift1,  key_in_r,    din_r,    din_valid_r,    r01_encrypt_out, r01_key_out, r01_dout, r01_dout_valid);
  ROUND02:  des_round port map (clk, reset, stall, r01_encrypt_out, encrypt_shift2,  decrypt_shift2,  r01_key_out, r01_dout, r01_dout_valid, r02_encrypt_out, r02_key_out, r02_dout, r02_dout_valid);
  ROUND03:  des_round port map (clk, reset, stall, r02_encrypt_out, encrypt_shift3,  decrypt_shift3,  r02_key_out, r02_dout, r02_dout_valid, r03_encrypt_out, r03_key_out, r03_dout, r03_dout_valid);
  ROUND04:  des_round port map (clk, reset, stall, r03_encrypt_out, encrypt_shift4,  decrypt_shift4,  r03_key_out, r03_dout, r03_dout_valid, r04_encrypt_out, r04_key_out, r04_dout, r04_dout_valid);
  ROUND05:  des_round port map (clk, reset, stall, r04_encrypt_out, encrypt_shift5,  decrypt_shift5,  r04_key_out, r04_dout, r04_dout_valid, r05_encrypt_out, r05_key_out, r05_dout, r05_dout_valid);
  ROUND06:  des_round port map (clk, reset, stall, r05_encrypt_out, encrypt_shift6,  decrypt_shift6,  r05_key_out, r05_dout, r05_dout_valid, r06_encrypt_out, r06_key_out, r06_dout, r06_dout_valid);
  ROUND07:  des_round port map (clk, reset, stall, r06_encrypt_out, encrypt_shift7,  decrypt_shift7,  r06_key_out, r06_dout, r06_dout_valid, r07_encrypt_out, r07_key_out, r07_dout, r07_dout_valid);
  ROUND08:  des_round port map (clk, reset, stall, r07_encrypt_out, encrypt_shift8,  decrypt_shift8,  r07_key_out, r07_dout, r07_dout_valid, r08_encrypt_out, r08_key_out, r08_dout, r08_dout_valid);
  ROUND09:  des_round port map (clk, reset, stall, r08_encrypt_out, encrypt_shift9,  decrypt_shift9,  r08_key_out, r08_dout, r08_dout_valid, r09_encrypt_out, r09_key_out, r09_dout, r09_dout_valid);
  ROUND10:  des_round port map (clk, reset, stall, r09_encrypt_out, encrypt_shift10, decrypt_shift10, r09_key_out, r09_dout, r09_dout_valid, r10_encrypt_out, r10_key_out, r10_dout, r10_dout_valid);
  ROUND11:  des_round port map (clk, reset, stall, r10_encrypt_out, encrypt_shift11, decrypt_shift11, r10_key_out, r10_dout, r10_dout_valid, r11_encrypt_out, r11_key_out, r11_dout, r11_dout_valid);
  ROUND12:  des_round port map (clk, reset, stall, r11_encrypt_out, encrypt_shift12, decrypt_shift12, r11_key_out, r11_dout, r11_dout_valid, r12_encrypt_out, r12_key_out, r12_dout, r12_dout_valid);
  ROUND13:  des_round port map (clk, reset, stall, r12_encrypt_out, encrypt_shift13, decrypt_shift13, r12_key_out, r12_dout, r12_dout_valid, r13_encrypt_out, r13_key_out, r13_dout, r13_dout_valid);
  ROUND14:  des_round port map (clk, reset, stall, r13_encrypt_out, encrypt_shift14, decrypt_shift14, r13_key_out, r13_dout, r13_dout_valid, r14_encrypt_out, r14_key_out, r14_dout, r14_dout_valid);
  ROUND15:  des_round port map (clk, reset, stall, r14_encrypt_out, encrypt_shift15, decrypt_shift15, r14_key_out, r14_dout, r14_dout_valid, r15_encrypt_out, r15_key_out, r15_dout, r15_dout_valid);
  ROUND16:  des_round port map (clk, reset, stall, r15_encrypt_out, encrypt_shift16, decrypt_shift16, r15_key_out, r15_dout, r15_dout_valid, r16_encrypt_out, r16_key_out, r16_dout,     dout_valid);

  dout <= des_fp(r16_dout(31 downto 0) & r16_dout(63 downto 32));
  key_out <= r16_key_out;
end arch_des_fast;


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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library work;
use work.des_lib.all;

entity des_small is
    port (clk		:in std_logic;
          reset		:in std_logic;

          encrypt	:in std_logic;
          key_in	:in std_logic_vector (55 downto 0);
          din		:in std_logic_vector (63 downto 0);
          din_valid	:in std_logic;
          
          busy		:buffer std_logic;
          dout		:out std_logic_vector (63 downto 0);
          dout_valid	:out std_logic
         );
end des_small;


architecture arch_des_small of des_small is
  type STATES is (IDLE, WORKING);
  signal state  	:STATES := IDLE;
  signal round		:std_logic_vector (3 downto 0) := "0000";
  signal stall		:std_logic := '0';

  signal key		:std_logic_vector (55 downto 0) := "00000000000000000000000000000000000000000000000000000000";
  signal encrypt_flag	:std_logic := '1'; 

  signal encrypt_in	:std_logic := '1';
  signal encrypt_shift	:std_logic_vector (4 downto 0) := "00000";
  signal decrypt_shift	:std_logic_vector (4 downto 0) := "00000";
  signal r_key_in	:std_logic_vector (55 downto 0) := "00000000000000000000000000000000000000000000000000000000";
  signal r_din		:std_logic_vector (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
  
  signal r_dout		:std_logic_vector (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";
  signal dummy1		:std_logic := '0';
  signal dummy2 	:std_logic := '0';
  signal dummy3 	:std_logic := '0';
  signal dummy4 	:std_logic_vector (55 downto 0) := "00000000000000000000000000000000000000000000000000000000";
begin

  -- Manage the IDLE/WORKING state machine
  process (clk, reset, round, din_valid)
  begin
    if reset='1' then
      state <= IDLE;
    elsif clk'event and clk='1' then
      case state is
        when IDLE =>
            if din_valid='1' then
              state <= WORKING;
            end if;

        when WORKING =>
            if (round="1111") then
              state <= IDLE;
            end if;
      end case;
    end if;
  end process;

  -- Track the current DES round
  process (clk, reset, din_valid, state)
  begin
    if reset='1' then
      round <= "0000";
    elsif clk'event and clk='1' then
      if state/=IDLE then
        round <= round + 1;
      elsif din_valid='1' then
        round <= round + 1;
      else
        round <= "0000";
      end if;
    end if;
  end process;

  -- Generate the busy signal
  process (clk, reset, state, round, din_valid)
  begin
    if reset='1' then
      busy <= '0';
    elsif clk'event and clk='1' then
      if state=IDLE and din_valid='0' then
        busy <= '0';
      elsif round="1111" then
        busy <= '0';
      else
        busy <= '1';
      end if;
    end if;
  end process;


  -- Latch the encrypt_flag, key
  process (clk, reset, state, din_valid, encrypt, key_in)
  begin
    if reset='1' then
      encrypt_flag <= '0';
      key <= "00000000000000000000000000000000000000000000000000000000";
    elsif clk'event and clk='1' then
      if state=IDLE and din_valid='1' then
        encrypt_flag <= encrypt;
        key <= key_in;
      end if;
    end if;
  end process;

  -- Mux the inputs to des_round
  encrypt_in <= encrypt when state=IDLE else encrypt_flag;
  r_key_in <= key_in when state=IDLE else key;
  r_din <= des_ip(din) when state=IDLE else r_dout;
  dummy1 <= '0';
  stall <= '0';

  -- Do the round
  ROUND0: des_round port map (clk, reset, stall,
               encrypt_in, encrypt_shift, decrypt_shift,
               r_key_in, r_din, dummy1,
               dummy2, dummy4, r_dout, dummy3);


  -- Generate the encrypt/decrypt key shift amounts:
  process (round)
  begin
    case round is
      when "0000" =>  encrypt_shift <= "00001"; decrypt_shift <= "00000";
      when "0001" =>  encrypt_shift <= "00010"; decrypt_shift <= "11011";
      when "0010" =>  encrypt_shift <= "00100"; decrypt_shift <= "11001";
      when "0011" =>  encrypt_shift <= "00110"; decrypt_shift <= "10111";
      when "0100" =>  encrypt_shift <= "01000"; decrypt_shift <= "10101";
      when "0101" =>  encrypt_shift <= "01010"; decrypt_shift <= "10011";
      when "0110" =>  encrypt_shift <= "01100"; decrypt_shift <= "10001";
      when "0111" =>  encrypt_shift <= "01110"; decrypt_shift <= "01111";
      when "1000" =>  encrypt_shift <= "01111"; decrypt_shift <= "01110";
      when "1001" =>  encrypt_shift <= "10001"; decrypt_shift <= "01100";
      when "1010" =>  encrypt_shift <= "10011"; decrypt_shift <= "01010";
      when "1011" =>  encrypt_shift <= "10101"; decrypt_shift <= "01000";
      when "1100" =>  encrypt_shift <= "10111"; decrypt_shift <= "00110";
      when "1101" =>  encrypt_shift <= "11001"; decrypt_shift <= "00100";
      when "1110" =>  encrypt_shift <= "11011"; decrypt_shift <= "00010";
      when "1111" =>  encrypt_shift <= "00000"; decrypt_shift <= "00001";
      when others =>  encrypt_shift <= "00001"; decrypt_shift <= "00000";
    end case;
  end process;

  -- Generate the dout_valid signal
  process (clk, reset, round)
  begin
    if reset='1' then
      dout_valid <= '0';
    elsif clk'event and clk='1' then
      if round="1111" then
        dout_valid <= '1';
      else
        dout_valid <= '0';
      end if;      
    end if;
  end process;

  -- Output the data
  dout <= des_fp(r_dout(31 downto 0) & r_dout(63 downto 32));

end arch_des_small;


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