dtt6c03b_zsp0_h.lex

此源码是基于大唐微电子的DSP芯片ZSP的串口程序

GSMIF_INT_EN_REG_H|dg|#define GSMIF_INT_EN_REG_H((GSMIF_BASE + 0x9)||1069|
GSMIF_INT_EN_REG_L|dg|#define GSMIF_INT_EN_REG_L((GSMIF_BASE + 0x8)||1068|
GSMIF_INT_ORI_STATUS|dg|#define GSMIF_INT_ORI_STATUS((GSMIF_BASE + 0xC)||1073|
GSMIF_INT_STATUS_REG_H|dg|#define GSMIF_INT_STATUS_REG_H((GSMIF_BASE + 0xB)||1072|
GSMIF_INT_STATUS_REG_L|dg|#define GSMIF_INT_STATUS_REG_L((GSMIF_BASE + 0xA)||1071|
GSMIF_INT_STATUS_REG|dg|#define GSMIF_INT_STATUS_REG((GSMIF_BASE + 0xA)||1070|
GSMIF_RFAF_INT|dg|#define GSMIF_RFAF_INT||1138|
GSMIF_RFHF_INT|dg|#define GSMIF_RFHF_INT||1139|
GSMIF_RFNE_INT|dg|#define GSMIF_RFNE_INT||1140|
GSMIF_RF_RERR_INT|dg|#define GSMIF_RF_RERR_INT||1135|
GSMIF_RF_WERR_INT|dg|#define GSMIF_RF_WERR_INT||1134|
GSMIF_RX_FIFO|dg|#define GSMIF_RX_FIFO((GSMIF_BASE + 0x18)||1079|
GSMIF_SPI0_TX_FIFO|dg|#define GSMIF_SPI0_TX_FIFO((GSMIF_BASE + 0x20)||1081|
GSMIF_SPI1_TX_FIFO|dg|#define GSMIF_SPI1_TX_FIFO((GSMIF_BASE + 0x22)||1082|
GSMIF_SPI_CTRL_REG_EVT_SPI_ENB|dg|#define GSMIF_SPI_CTRL_REG_EVT_SPI_ENB||1159|
GSMIF_SPI_CTRL_REG_SPI_ENB|dg|#define GSMIF_SPI_CTRL_REG_SPI_ENB||1158|
GSMIF_SPI_CTRL_REG_XCHB|dg|#define GSMIF_SPI_CTRL_REG_XCHB||1160|
GSMIF_SPI_CTRL_REG|dg|#define GSMIF_SPI_CTRL_REG((GSMIF_BASE + 0x26)||1084|
GSMIF_SPI_PARA_REG_H|dg|#define GSMIF_SPI_PARA_REG_H((GSMIF_BASE + 0x29)||1086|
GSMIF_SPI_PARA_REG_L|dg|#define GSMIF_SPI_PARA_REG_L((GSMIF_BASE + 0x28)||1085|
GSMIF_SPI_PARA_REG_SPI_ADDIB|dg|#define GSMIF_SPI_PARA_REG_SPI_ADDIB||1173|
GSMIF_SPI_PARA_REG_SPI_DATARATEBF|dg|#define GSMIF_SPI_PARA_REG_SPI_DATARATEBF||1163|
GSMIF_SPI_PARA_REG_SPI_DATARATE_128|dg|#define GSMIF_SPI_PARA_REG_SPI_DATARATE_128||1169|
GSMIF_SPI_PARA_REG_SPI_DATARATE_16|dg|#define GSMIF_SPI_PARA_REG_SPI_DATARATE_16||1166|
GSMIF_SPI_PARA_REG_SPI_DATARATE_256|dg|#define GSMIF_SPI_PARA_REG_SPI_DATARATE_256||1170|
GSMIF_SPI_PARA_REG_SPI_DATARATE_32|dg|#define GSMIF_SPI_PARA_REG_SPI_DATARATE_32||1167|
GSMIF_SPI_PARA_REG_SPI_DATARATE_4|dg|#define GSMIF_SPI_PARA_REG_SPI_DATARATE_4||1164|
GSMIF_SPI_PARA_REG_SPI_DATARATE_512|dg|#define GSMIF_SPI_PARA_REG_SPI_DATARATE_512||1171|
GSMIF_SPI_PARA_REG_SPI_DATARATE_64|dg|#define GSMIF_SPI_PARA_REG_SPI_DATARATE_64||1168|
GSMIF_SPI_PARA_REG_SPI_DATARATE_8|dg|#define GSMIF_SPI_PARA_REG_SPI_DATARATE_8||1165|
GSMIF_SPI_PARA_REG_SPI_PHAB|dg|#define GSMIF_SPI_PARA_REG_SPI_PHAB||1175|
GSMIF_SPI_PARA_REG_SPI_PHA_0|dg|#define GSMIF_SPI_PARA_REG_SPI_PHA_0||1177|
GSMIF_SPI_PARA_REG_SPI_PHA_1|dg|#define GSMIF_SPI_PARA_REG_SPI_PHA_1||1176|
GSMIF_SPI_PARA_REG_SPI_POLB|dg|#define GSMIF_SPI_PARA_REG_SPI_POLB||1179|
GSMIF_SPI_PARA_REG_SPI_POL_0|dg|#define GSMIF_SPI_PARA_REG_SPI_POL_0||1181|
GSMIF_SPI_PARA_REG_SPI_POL_1|dg|#define GSMIF_SPI_PARA_REG_SPI_POL_1||1180|
GSMIF_SPI_PARA_REG_SPI_WORD_LENGTHBF|dg|#define GSMIF_SPI_PARA_REG_SPI_WORD_LENGTHBF||1183|
GSMIF_SPI_RFAF_INT|dg|#define GSMIF_SPI_RFAF_INT||1127|
GSMIF_SPI_RFHF_INT|dg|#define GSMIF_SPI_RFHF_INT||1128|
GSMIF_SPI_RFNE_INT|dg|#define GSMIF_SPI_RFNE_INT||1129|
GSMIF_SPI_RF_RERR_INT|dg|#define GSMIF_SPI_RF_RERR_INT||1124|
GSMIF_SPI_RF_WERR_INT|dg|#define GSMIF_SPI_RF_WERR_INT||1123|
GSMIF_SPI_RST_REG_SPI_RSTB|dg|#define GSMIF_SPI_RST_REG_SPI_RSTB||1185|
GSMIF_SPI_RST_REG|dg|#define GSMIF_SPI_RST_REG((GSMIF_BASE + 0x2C)||1088|
GSMIF_SPI_RX_FIFO|dg|#define GSMIF_SPI_RX_FIFO((GSMIF_BASE + 0x24)||1083|
GSMIF_SPI_TFAE_INT|dg|#define GSMIF_SPI_TFAE_INT||1132|
GSMIF_SPI_TFHE_INT|dg|#define GSMIF_SPI_TFHE_INT||1131|
GSMIF_SPI_TFNF_INT|dg|#define GSMIF_SPI_TFNF_INT||1130|
GSMIF_SPI_TF_RERR_INT|dg|#define GSMIF_SPI_TF_RERR_INT||1126|
GSMIF_SPI_TF_WERR_INT|dg|#define GSMIF_SPI_TF_WERR_INT||1125|
GSMIF_SPI_WAIT_REG|dg|#define GSMIF_SPI_WAIT_REG((GSMIF_BASE + 0x2A)||1087|
GSMIF_TFAE_INT|dg|#define GSMIF_TFAE_INT||1143|
GSMIF_TFHE_INT|dg|#define GSMIF_TFHE_INT||1142|
GSMIF_TFNF_INT|dg|#define GSMIF_TFNF_INT||1141|
GSMIF_TF_RERR_INT|dg|#define GSMIF_TF_RERR_INT||1137|
GSMIF_TF_WERR_INT|dg|#define GSMIF_TF_WERR_INT||1136|
GSMIF_TIMER_ADJ_REG|dg|#define GSMIF_TIMER_ADJ_REG((GSMIF_BASE + 0x02)||1064|
GSMIF_TIMER_CTRL_REG_DATA_CLK_SWITCHB|dg|#define GSMIF_TIMER_CTRL_REG_DATA_CLK_SWITCHB||1117|
GSMIF_TIMER_CTRL_REG_RXF_CLRB|dg|#define GSMIF_TIMER_CTRL_REG_RXF_CLRB||1112|
GSMIF_TIMER_CTRL_REG_SAMPLE_PHASEBF|dg|#define GSMIF_TIMER_CTRL_REG_SAMPLE_PHASEBF||1115|
GSMIF_TIMER_CTRL_REG_TIMER_ENB|dg|#define GSMIF_TIMER_CTRL_REG_TIMER_ENB||1114|
GSMIF_TIMER_CTRL_REG_TXF_CLRB|dg|#define GSMIF_TIMER_CTRL_REG_TXF_CLRB||1113|
GSMIF_TIMER_CTRL_REG|dg|#define GSMIF_TIMER_CTRL_REG((GSMIF_BASE + 0x06)||1067|
GSMIF_TIMER_RETURN_REG|dg|#define GSMIF_TIMER_RETURN_REG((GSMIF_BASE + 0x00)||1063|
GSMIF_TIMER_VALUE_REG_H|dg|#define GSMIF_TIMER_VALUE_REG_H((GSMIF_BASE + 0x05)||1066|
GSMIF_TIMER_VALUE_REG_L|dg|#define GSMIF_TIMER_VALUE_REG_L((GSMIF_BASE + 0x04)||1065|
GSMIF_TIMER_VALUE_REG_TIMER_SLEEP_STATUSB|dg|#define GSMIF_TIMER_VALUE_REG_TIMER_SLEEP_STATUSB||1106|
GSMIF_TIMER_VALUE_REG_TIMER_SLEEP_STATUS_SLEEP|dg|#define GSMIF_TIMER_VALUE_REG_TIMER_SLEEP_STATUS_SLEEP||1107|
GSMIF_TIMER_VALUE_REG_TIMER_SLEEP_STATUS_WORK|dg|#define GSMIF_TIMER_VALUE_REG_TIMER_SLEEP_STATUS_WORK||1108|
GSMIF_TIMER_VALUE_REG_TIMER_VALBF|dg|#define GSMIF_TIMER_VALUE_REG_TIMER_VALBF||1110|
GSMIF_TX_FIFO|dg|#define GSMIF_TX_FIFO((GSMIF_BASE + 0x1A)||1080|
I2C_BASE|dg|#define I2C_BASE||49|
I2S_BASE|dg|#define I2S_BASE||33|
JD_BASE|dg|#define JD_BASE||27|
LCDC_BASE|dg|#define LCDC_BASE||38|
MMC_BASE|dg|#define MMC_BASE||46|
MPEGA_BASE|dg|#define MPEGA_BASE||24|
NFC_BASE|dg|#define NFC_BASE||43|
RELATE_BASE|dg|#define RELATE_BASE||26|
SHARM_BASE|dg|#define SHARM_BASE||37|
SSI0_BASE|dg|#define SSI0_BASE||45|
SSI1_BASE|dg|#define SSI1_BASE||34|
TDIF_BASE|dg|#define TDIF_BASE||18|
TDIF_EVENT0_ITEM0|dg|#define TDIF_EVENT0_ITEM0((TDIF_BASE + 0x80)||921|
TDIF_EVENT0_ITEM1|dg|#define TDIF_EVENT0_ITEM1((TDIF_BASE + 0x82)||922|
TDIF_EVENT0_ITEM2|dg|#define TDIF_EVENT0_ITEM2((TDIF_BASE + 0x84)||923|
TDIF_EVENT0_ITEM3|dg|#define TDIF_EVENT0_ITEM3((TDIF_BASE + 0x86)||924|
TDIF_EVENT0_ITEM4|dg|#define TDIF_EVENT0_ITEM4((TDIF_BASE + 0x88)||925|
TDIF_EVENT0_ITEM5|dg|#define TDIF_EVENT0_ITEM5((TDIF_BASE + 0x8A)||926|
TDIF_EVENT0_ITEM6|dg|#define TDIF_EVENT0_ITEM6((TDIF_BASE + 0x8C)||927|
TDIF_EVENT0_ITEM7|dg|#define TDIF_EVENT0_ITEM7((TDIF_BASE + 0x8E)||928|
TDIF_EVENT1_ITEM0|dg|#define TDIF_EVENT1_ITEM0((TDIF_BASE + 0x100)||929|
TDIF_EVENT1_ITEM1|dg|#define TDIF_EVENT1_ITEM1((TDIF_BASE + 0x102)||930|
TDIF_EVENT1_ITEM2|dg|#define TDIF_EVENT1_ITEM2((TDIF_BASE + 0x104)||931|
TDIF_EVENT1_ITEM3|dg|#define TDIF_EVENT1_ITEM3((TDIF_BASE + 0x106)||932|
TDIF_EVENT1_ITEM4|dg|#define TDIF_EVENT1_ITEM4((TDIF_BASE + 0x108)||933|
TDIF_EVENT1_ITEM5|dg|#define TDIF_EVENT1_ITEM5((TDIF_BASE + 0x10A)||934|
TDIF_EVENT1_ITEM62|dg|#define TDIF_EVENT1_ITEM62((TDIF_BASE + 0x17C)||937|
TDIF_EVENT1_ITEM63|dg|#define TDIF_EVENT1_ITEM63((TDIF_BASE + 0x17E)||938|
TDIF_EVENT1_ITEM6|dg|#define TDIF_EVENT1_ITEM6((TDIF_BASE + 0x10C)||935|
TDIF_EVENT1_ITEM7|dg|#define TDIF_EVENT1_ITEM7((TDIF_BASE + 0x10E)||936|
TDIF_EVENT_CTRL_REG_EVT_ENB|dg|#define TDIF_EVENT_CTRL_REG_EVT_ENB||988|
TDIF_EVENT_CTRL_REG_EVT_STATB|dg|#define TDIF_EVENT_CTRL_REG_EVT_STATB||984|
TDIF_EVENT_CTRL_REG_EVT_STAT_IDLE|dg|#define TDIF_EVENT_CTRL_REG_EVT_STAT_IDLE||986|
TDIF_EVENT_CTRL_REG_EVT_STAT_WORK|dg|#define TDIF_EVENT_CTRL_REG_EVT_STAT_WORK||985|
TDIF_EVENT_CTRL_REG_H|dg|#define TDIF_EVENT_CTRL_REG_H((TDIF_BASE + 0x11)||898|
TDIF_EVENT_CTRL_REG_L|dg|#define TDIF_EVENT_CTRL_REG_L((TDIF_BASE + 0x10)||897|
TDIF_EVENT_INT_INDEX|dg|#define TDIF_EVENT_INT_INDEX((TDIF_BASE + 0x14)||900|
TDIF_EVENT_STATUS_REG_EVENT0_STATUSB|dg|#define TDIF_EVENT_STATUS_REG_EVENT0_STATUSB||991|
TDIF_EVENT_STATUS_REG_EVENT1_STATUSB|dg|#define TDIF_EVENT_STATUS_REG_EVENT1_STATUSB||992|
TDIF_EVENT_STATUS_REG_EVENT_STATUS_ACTIVE|dg|#define TDIF_EVENT_STATUS_REG_EVENT_STATUS_ACTIVE||993|
TDIF_EVENT_STATUS_REG_EVENT_STATUS_UPDATE|dg|#define TDIF_EVENT_STATUS_REG_EVENT_STATUS_UPDATE||994|
TDIF_EVENT_STATUS_REG_INDEXBF|dg|#define TDIF_EVENT_STATUS_REG_INDEXBF||996|
TDIF_EVENT_STATUS_REG|dg|#define TDIF_EVENT_STATUS_REG((TDIF_BASE + 0x12)||899|
TDIF_EVT_CFGE_INT|dg|#define TDIF_EVT_CFGE_INT||958|
TDIF_EVT_EXE_INT|dg|#define TDIF_EVT_EXE_INT||960|
TDIF_EVT_SW_INT|dg|#define TDIF_EVT_SW_INT||959|
TDIF_FIR_CTRL_REG_AD_CUT_POSITIONBF|dg|#define TDIF_FIR_CTRL_REG_AD_CUT_POSITIONBF||1022|
TDIF_FIR_CTRL_REG_AD_DPRAM_ADD_CLRB|dg|#define TDIF_FIR_CTRL_REG_AD_DPRAM_ADD_CLRB||1000|
TDIF_FIR_CTRL_REG_AD_FIR_BPB|dg|#define TDIF_FIR_CTRL_REG_AD_FIR_BPB||1007|
TDIF_FIR_CTRL_REG_CUT_POSITION_0|dg|#define TDIF_FIR_CTRL_REG_CUT_POSITION_0||1024|
TDIF_FIR_CTRL_REG_CUT_POSITION_1|dg|#define TDIF_FIR_CTRL_REG_CUT_POSITION_1||1025|
TDIF_FIR_CTRL_REG_CUT_POSITION_2|dg|#define TDIF_FIR_CTRL_REG_CUT_POSITION_2||1026|
TDIF_FIR_CTRL_REG_DA_CUT_POSITIONBF|dg|#define TDIF_FIR_CTRL_REG_DA_CUT_POSITIONBF||1023|
TDIF_FIR_CTRL_REG_DA_DPRAM_ADD_CLRB|dg|#define TDIF_FIR_CTRL_REG_DA_DPRAM_ADD_CLRB||1001|
TDIF_FIR_CTRL_REG_DA_FIR_BPB|dg|#define TDIF_FIR_CTRL_REG_DA_FIR_BPB||1008|
TDIF_FIR_CTRL_REG_H|dg|#define TDIF_FIR_CTRL_REG_H((TDIF_BASE + 0x29)||906|
TDIF_FIR_CTRL_REG_LOOP_MODEB|dg|#define TDIF_FIR_CTRL_REG_LOOP_MODEB||1003|
TDIF_FIR_CTRL_REG_LOOP_MODE_LOOP|dg|#define TDIF_FIR_CTRL_REG_LOOP_MODE_LOOP||1004|
TDIF_FIR_CTRL_REG_LOOP_MODE_NORMAL|dg|#define TDIF_FIR_CTRL_REG_LOOP_MODE_NORMAL||1005|
TDIF_FIR_CTRL_REG_L|dg|#define TDIF_FIR_CTRL_REG_L((TDIF_BASE + 0x28)||905|
TDIF_FIR_CTRL_REG_RETURNBF|dg|#define TDIF_FIR_CTRL_REG_RETURNBF||1020|
TDIF_FIR_CTRL_REG_RFIR_MODEB|dg|#define TDIF_FIR_CTRL_REG_RFIR_MODEB||1010|
TDIF_FIR_CTRL_REG_RFIR_MODE_0|dg|#define TDIF_FIR_CTRL_REG_RFIR_MODE_0||1012|
TDIF_FIR_CTRL_REG_RFIR_MODE_1|dg|#define TDIF_FIR_CTRL_REG_RFIR_MODE_1||1011|
TDIF_FIR_CTRL_REG_RFIR_PHASEBF|dg|#define TDIF_FIR_CTRL_REG_RFIR_PHASEBF||1014|
TDIF_FIR_CTRL_REG_RFIR_PHASE_0|dg|#define TDIF_FIR_CTRL_REG_RFIR_PHASE_0||1015|
TDIF_FIR_CTRL_REG_RFIR_PHASE_1|dg|#define TDIF_FIR_CTRL_REG_RFIR_PHASE_1||1016|
TDIF_FIR_CTRL_REG_RFIR_PHASE_2|dg|#define TDIF_FIR_CTRL_REG_RFIR_PHASE_2||1017|
TDIF_FIR_CTRL_REG_RFIR_PHASE_3|dg|#define TDIF_FIR_CTRL_REG_RFIR_PHASE_3||1018|
TDIF_FIR_CTRL_REG_RX_FIR_CLRB|dg|#define TDIF_FIR_CTRL_REG_RX_FIR_CLRB||998|
TDIF_FIR_CTRL_REG_TX_FIR_CLRB|dg|#define TDIF_FIR_CTRL_REG_TX_FIR_CLRB||999|
TDIF_FIR_MAXDA_REG_CLR_MEASUREB|dg|#define TDIF_FIR_MAXDA_REG_CLR_MEASUREB||1029|
TDIF_FIR_MAXDA_REG_MAX_DA_I_DATABF|dg|#define TDIF_FIR_MAXDA_REG_MAX_DA_I_DATABF||1030|
TDIF_FIR_MAXDA_REG_MEASURE_ENB|dg|#define TDIF_FIR_MAXDA_REG_MEASURE_ENB||1028|
TDIF_FIR_MAXDA_REG|dg|#define TDIF_FIR_MAXDA_REG((TDIF_BASE + 0x2A)||908|
TDIF_FIR_PARA_REG|dg|#define TDIF_FIR_PARA_REG((TDIF_BASE + 0x20)||902|
TDIF_FIR_RX_FIFO|dg|#define TDIF_FIR_RX_FIFO((TDIF_BASE + 0x24)||904|
TDIF_FIR_TX_FIFO|dg|#define TDIF_FIR_TX_FIFO((TDIF_BASE + 0x22)||903|
TDIF_INT_EN_REG_H|dg|#define TDIF_INT_EN_REG_H((TDIF_BASE + 0x9)||889|
TDIF_INT_EN_REG_L|dg|#define TDIF_INT_EN_REG_L((TDIF_BASE + 0x8)||888|
TDIF_INT_ORI_STATUS|dg|#define TDIF_INT_ORI_STATUS((TDIF_BASE + 0xC)||895|
TDIF_INT_STATUS_REG_H|dg|#define TDIF_INT_STATUS_REG_H((TDIF_BASE + 0xB)||893|
TDIF_INT_STATUS_REG_L|dg|#define TDIF_INT_STATUS_REG_L((TDIF_BASE + 0xA)||892|
TDIF_INT_STATUS_REG|dg|#define TDIF_INT_STATUS_REG((TDIF_BASE + 0xA)||891|
TDIF_RFAF_INT|dg|#define TDIF_RFAF_INT||976|
TDIF_RFHF_INT|dg|#define TDIF_RFHF_INT||977|
TDIF_RFNE_INT|dg|#define TDIF_RFNE_INT||978|
TDIF_RF_RERR_INT|dg|#define TDIF_RF_RERR_INT||973|
TDIF_RF_WERR_INT|dg|#define TDIF_RF_WERR_INT||972|
TDIF_SPI0_PARA_REG|dg|#define TDIF_SPI0_PARA_REG((TDIF_BASE + 0x3A)||915|
TDIF_SPI0_TX_FIFO|dg|#define TDIF_SPI0_TX_FIFO((TDIF_BASE + 0x30)||910|
TDIF_SPI1_PARA_REG|dg|#define TDIF_SPI1_PARA_REG((TDIF_BASE + 0x3C)||916|
TDIF_SPI1_TX_FIFO|dg|#define TDIF_SPI1_TX_FIFO((TDIF_BASE + 0x32)||911|
TDIF_SPI2_PARA_REG|dg|#define TDIF_SPI2_PARA_REG((TDIF_BASE + 0x3E)||917|
TDIF_SPI2_TX_FIFO|dg|#define TDIF_SPI2_TX_FIFO((TDIF_BASE + 0x34)||912|
TDIF_SPI_CTRL_REG_EVT_SPI_ENB|dg|#define TDIF_SPI_CTRL_REG_EVT_SPI_ENB||1033|
TDIF_SPI_CTRL_REG_SPI_ENB|dg|#define TDIF_SPI_CTRL_REG_SPI_ENB||1032|
TDIF_SPI_CTRL_REG_XCHB|dg|#define TDIF_SPI_CTRL_REG_XCHB||1034|
TDIF_SPI_CTRL_REG|dg|#define TDIF_SPI_CTRL_REG((TDIF_BASE + 0x38)||914|
TDIF_SPI_PARA_REG_SPI_ADDIB|dg|#define TDIF_SPI_PARA_REG_SPI_ADDIB||1047|
TDIF_SPI_PARA_REG_SPI_DATARATEBF|dg|#define TDIF_SPI_PARA_REG_SPI_DATARATEBF||1037|
TDIF_SPI_PARA_REG_SPI_DATARATE_128|dg|#define TDIF_SPI_PARA_REG_SPI_DATARATE_128||1043|
TDIF_SPI_PARA_REG_SPI_DATARATE_16|dg|#define TDIF_SPI_PARA_REG_SPI_DATARATE_16||1040|
TDIF_SPI_PARA_REG_SPI_DATARATE_256|dg|#define TDIF_SPI_PARA_REG_SPI_DATARATE_256||1044|
TDIF_SPI_PARA_REG_SPI_DATARATE_32|dg|#define TDIF_SPI_PARA_REG_SPI_DATARATE_32||1041|
TDIF_SPI_PARA_REG_SPI_DATARATE_4|dg|#define TDIF_SPI_PARA_REG_SPI_DATARATE_4||1038|
TDIF_SPI_PARA_REG_SPI_DATARATE_512|dg|#define TDIF_SPI_PARA_REG_SPI_DATARATE_512||1045|
TDIF_SPI_PARA_REG_SPI_DATARATE_64|dg|#define TDIF_SPI_PARA_REG_SPI_DATARATE_64||1042|
TDIF_SPI_PARA_REG_SPI_DATARATE_8|dg|#define TDIF_SPI_PARA_REG_SPI_DATARATE_8||1039|
TDIF_SPI_PARA_REG_SPI_PHAB|dg|#define TDIF_SPI_PARA_REG_SPI_PHAB||1049|
TDIF_SPI_PARA_REG_SPI_PHA_0|dg|#define TDIF_SPI_PARA_REG_SPI_PHA_0||1051|
TDIF_SPI_PARA_REG_SPI_PHA_1|dg|#define TDIF_SPI_PARA_REG_SPI_PHA_1||1050|
TDIF_SPI_PARA_REG_SPI_POLB|dg|#define TDIF_SPI_PARA_REG_SPI_POLB||1053|
TDIF_SPI_PARA_REG_SPI_POL_0|dg|#define TDIF_SPI_PARA_REG_SPI_POL_0||1055|
TDIF_SPI_PARA_REG_SPI_POL_1|dg|#define TDIF_SPI_PARA_REG_SPI_POL_1||1054|
TDIF_SPI_PARA_REG_SPI_WORD_LENGTHBF|dg|#define TDIF_SPI_PARA_REG_SPI_WORD_LENGTHBF||1057|
TDIF_SPI_RFAF_INT|dg|#define TDIF_SPI_RFAF_INT||965|
TDIF_SPI_RFHF_INT|dg|#define TDIF_SPI_RFHF_INT||966|
TDIF_SPI_RFNE_INT|dg|#define TDIF_SPI_RFNE_INT||967|
TDIF_SPI_RF_RERR_INT|dg|#define TDIF_SPI_RF_RERR_INT||962|
TDIF_SPI_RF_WERR_INT|dg|#define TDIF_SPI_RF_WERR_INT||961|
TDIF_SPI_RST_REG_SPI_RSTB|dg|#define TDIF_SPI_RST_REG_SPI_RSTB||1059|
TDIF_SPI_RST_REG|dg|#define TDIF_SPI_RST_REG((TDIF_BASE + 0x42)||919|
TD