dtt6c03b_zsp0_h.lex

此源码是基于大唐微电子的DSP芯片ZSP的串口程序

DMAC0_SAR6|dg|#define DMAC0_SAR6((DMAC0_BASE + 0x108)||166|
DMAC0_SAR7|dg|#define DMAC0_SAR7((DMAC0_BASE + 0x134)||184|
DMAC0_SGLREQDSTREG|dg|#define DMAC0_SGLREQDSTREG((DMAC0_BASE + 0x1c0)||231|
DMAC0_SGLREQSRCREG|dg|#define DMAC0_SGLREQSRCREG((DMAC0_BASE + 0x1bc)||230|
DMAC0_SGR0_H|dg|#define DMAC0_SGR0_H((DMAC0_BASE + 0x025)||71|
DMAC0_SGR0_L|dg|#define DMAC0_SGR0_L((DMAC0_BASE + 0x024)||70|
DMAC0_SGR0|dg|#define DMAC0_SGR0((DMAC0_BASE + 0x024)||69|
DMAC0_SGR1_H|dg|#define DMAC0_SGR1_H((DMAC0_BASE + 0x051)||89|
DMAC0_SGR1_L|dg|#define DMAC0_SGR1_L((DMAC0_BASE + 0x050)||88|
DMAC0_SGR1|dg|#define DMAC0_SGR1((DMAC0_BASE + 0x050)||87|
DMAC0_SGR2_H|dg|#define DMAC0_SGR2_H((DMAC0_BASE + 0x07d)||107|
DMAC0_SGR2_L|dg|#define DMAC0_SGR2_L((DMAC0_BASE + 0x07c)||106|
DMAC0_SGR2|dg|#define DMAC0_SGR2((DMAC0_BASE + 0x07c)||105|
DMAC0_SGR3_H|dg|#define DMAC0_SGR3_H((DMAC0_BASE + 0x0a9)||125|
DMAC0_SGR3_L|dg|#define DMAC0_SGR3_L((DMAC0_BASE + 0x0a8)||124|
DMAC0_SGR3|dg|#define DMAC0_SGR3((DMAC0_BASE + 0x0a8)||123|
DMAC0_SGR4_H|dg|#define DMAC0_SGR4_H((DMAC0_BASE + 0x0d5)||143|
DMAC0_SGR4_L|dg|#define DMAC0_SGR4_L((DMAC0_BASE + 0x0d4)||142|
DMAC0_SGR4|dg|#define DMAC0_SGR4((DMAC0_BASE + 0x0d4)||141|
DMAC0_SGR5_H|dg|#define DMAC0_SGR5_H((DMAC0_BASE + 0x101)||161|
DMAC0_SGR5_L|dg|#define DMAC0_SGR5_L((DMAC0_BASE + 0x100)||160|
DMAC0_SGR5|dg|#define DMAC0_SGR5((DMAC0_BASE + 0x100)||159|
DMAC0_SGR6_H|dg|#define DMAC0_SGR6_H((DMAC0_BASE + 0x12d)||179|
DMAC0_SGR6_L|dg|#define DMAC0_SGR6_L((DMAC0_BASE + 0x12c)||178|
DMAC0_SGR6|dg|#define DMAC0_SGR6((DMAC0_BASE + 0x12c)||177|
DMAC0_SGR7_H|dg|#define DMAC0_SGR7_H((DMAC0_BASE + 0x159)||197|
DMAC0_SGR7_L|dg|#define DMAC0_SGR7_L((DMAC0_BASE + 0x158)||196|
DMAC0_SGR7|dg|#define DMAC0_SGR7((DMAC0_BASE + 0x158)||195|
DMAC0_STATUSBLOCK|dg|#define DMAC0_STATUSBLOCK((DMAC0_BASE + 0x178)||209|
DMAC0_STATUSDSTTRAN|dg|#define DMAC0_STATUSDSTTRAN((DMAC0_BASE + 0x180)||211|
DMAC0_STATUSERR|dg|#define DMAC0_STATUSERR((DMAC0_BASE + 0x184)||212|
DMAC0_STATUSINT|dg|#define DMAC0_STATUSINT((DMAC0_BASE + 0x1b0)||226|
DMAC0_STATUSSRCTRAN|dg|#define DMAC0_STATUSSRCTRAN((DMAC0_BASE + 0x17c)||210|
DMAC0_STATUSTFR|dg|#define DMAC0_STATUSTFR((DMAC0_BASE + 0x174)||208|
DMAC1_BASE|dg|#define DMAC1_BASE||21|
DMAC1_CFG0_0|dg|#define DMAC1_CFG0_0((DMAC1_BASE + 0x020)||248|
DMAC1_CFG0_1|dg|#define DMAC1_CFG0_1((DMAC1_BASE + 0x021)||249|
DMAC1_CFG0_2|dg|#define DMAC1_CFG0_2((DMAC1_BASE + 0x022)||250|
DMAC1_CFG0|dg|#define DMAC1_CFG0((DMAC1_BASE + 0x020)||247|
DMAC1_CFG1_0|dg|#define DMAC1_CFG1_0((DMAC1_BASE + 0x04c)||266|
DMAC1_CFG1_1|dg|#define DMAC1_CFG1_1((DMAC1_BASE + 0x04d)||267|
DMAC1_CFG1_2|dg|#define DMAC1_CFG1_2((DMAC1_BASE + 0x04e)||268|
DMAC1_CFG1|dg|#define DMAC1_CFG1((DMAC1_BASE + 0x04c)||265|
DMAC1_CFG2_0|dg|#define DMAC1_CFG2_0((DMAC1_BASE + 0x078)||284|
DMAC1_CFG2_1|dg|#define DMAC1_CFG2_1((DMAC1_BASE + 0x079)||285|
DMAC1_CFG2_2|dg|#define DMAC1_CFG2_2((DMAC1_BASE + 0x07a)||286|
DMAC1_CFG2|dg|#define DMAC1_CFG2((DMAC1_BASE + 0x078)||283|
DMAC1_CFG3_0|dg|#define DMAC1_CFG3_0((DMAC1_BASE + 0x0a4)||302|
DMAC1_CFG3_1|dg|#define DMAC1_CFG3_1((DMAC1_BASE + 0x0a5)||303|
DMAC1_CFG3_2|dg|#define DMAC1_CFG3_2((DMAC1_BASE + 0x0a6)||304|
DMAC1_CFG3|dg|#define DMAC1_CFG3((DMAC1_BASE + 0x0a4)||301|
DMAC1_CFG4_0|dg|#define DMAC1_CFG4_0((DMAC1_BASE + 0x0d0)||320|
DMAC1_CFG4_1|dg|#define DMAC1_CFG4_1((DMAC1_BASE + 0x0d1)||321|
DMAC1_CFG4_2|dg|#define DMAC1_CFG4_2((DMAC1_BASE + 0x0d2)||322|
DMAC1_CFG4|dg|#define DMAC1_CFG4((DMAC1_BASE + 0x0d0)||319|
DMAC1_CFG5_0|dg|#define DMAC1_CFG5_0((DMAC1_BASE + 0x0fc)||338|
DMAC1_CFG5_1|dg|#define DMAC1_CFG5_1((DMAC1_BASE + 0x0fd)||339|
DMAC1_CFG5_2|dg|#define DMAC1_CFG5_2((DMAC1_BASE + 0x0fe)||340|
DMAC1_CFG5|dg|#define DMAC1_CFG5((DMAC1_BASE + 0x0fc)||337|
DMAC1_CFG_2_DEST_PER_GSM_RX|dg|#define DMAC1_CFG_2_DEST_PER_GSM_RX||444|
DMAC1_CFG_2_DEST_PER_GSM_TX|dg|#define DMAC1_CFG_2_DEST_PER_GSM_TX||436|
DMAC1_CFG_2_DEST_PER_I2S_RX|dg|#define DMAC1_CFG_2_DEST_PER_I2S_RX||445|
DMAC1_CFG_2_DEST_PER_I2S_TX|dg|#define DMAC1_CFG_2_DEST_PER_I2S_TX||437|
DMAC1_CFG_2_DEST_PER_MPEGA_IDCT_RX|dg|#define DMAC1_CFG_2_DEST_PER_MPEGA_IDCT_RX||447|
DMAC1_CFG_2_DEST_PER_MPEGA_IDCT_TX|dg|#define DMAC1_CFG_2_DEST_PER_MPEGA_IDCT_TX||439|
DMAC1_CFG_2_DEST_PER_MPEGA_MC_TX|dg|#define DMAC1_CFG_2_DEST_PER_MPEGA_MC_TX||440|
DMAC1_CFG_2_DEST_PER_TD_RX|dg|#define DMAC1_CFG_2_DEST_PER_TD_RX||443|
DMAC1_CFG_2_DEST_PER_TD_TX|dg|#define DMAC1_CFG_2_DEST_PER_TD_TX||435|
DMAC1_CFG_2_DEST_PER_UART2_RX|dg|#define DMAC1_CFG_2_DEST_PER_UART2_RX||446|
DMAC1_CFG_2_DEST_PER_UART2_TX|dg|#define DMAC1_CFG_2_DEST_PER_UART2_TX||438|
DMAC1_CHENREG|dg|#define DMAC1_CHENREG((DMAC1_BASE + 0x1d0)||381|
DMAC1_CLEARBLOCK|dg|#define DMAC1_CLEARBLOCK((DMAC1_BASE + 0x1a0)||368|
DMAC1_CLEARDSTTRAN|dg|#define DMAC1_CLEARDSTTRAN((DMAC1_BASE + 0x1a8)||370|
DMAC1_CLEARERR|dg|#define DMAC1_CLEARERR((DMAC1_BASE + 0x1ac)||371|
DMAC1_CLEARSRCTRAN|dg|#define DMAC1_CLEARSRCTRAN((DMAC1_BASE + 0x1a4)||369|
DMAC1_CLEARTFR|dg|#define DMAC1_CLEARTFR((DMAC1_BASE + 0x19c)||367|
DMAC1_CTL0_0|dg|#define DMAC1_CTL0_0((DMAC1_BASE + 0x00c)||244|
DMAC1_CTL0_1|dg|#define DMAC1_CTL0_1((DMAC1_BASE + 0x00d)||245|
DMAC1_CTL0_2|dg|#define DMAC1_CTL0_2((DMAC1_BASE + 0x00e)||246|
DMAC1_CTL0|dg|#define DMAC1_CTL0((DMAC1_BASE + 0x00c)||243|
DMAC1_CTL1_0|dg|#define DMAC1_CTL1_0((DMAC1_BASE + 0x038)||262|
DMAC1_CTL1_1|dg|#define DMAC1_CTL1_1((DMAC1_BASE + 0x039)||263|
DMAC1_CTL1_2|dg|#define DMAC1_CTL1_2((DMAC1_BASE + 0x03a)||264|
DMAC1_CTL1|dg|#define DMAC1_CTL1((DMAC1_BASE + 0x038)||261|
DMAC1_CTL2_0|dg|#define DMAC1_CTL2_0((DMAC1_BASE + 0x064)||280|
DMAC1_CTL2_1|dg|#define DMAC1_CTL2_1((DMAC1_BASE + 0x065)||281|
DMAC1_CTL2_2|dg|#define DMAC1_CTL2_2((DMAC1_BASE + 0x066)||282|
DMAC1_CTL2|dg|#define DMAC1_CTL2((DMAC1_BASE + 0x064)||279|
DMAC1_CTL3_0|dg|#define DMAC1_CTL3_0((DMAC1_BASE + 0x090)||298|
DMAC1_CTL3_1|dg|#define DMAC1_CTL3_1((DMAC1_BASE + 0x091)||299|
DMAC1_CTL3_2|dg|#define DMAC1_CTL3_2((DMAC1_BASE + 0x092)||300|
DMAC1_CTL3|dg|#define DMAC1_CTL3((DMAC1_BASE + 0x090)||297|
DMAC1_CTL4_0|dg|#define DMAC1_CTL4_0((DMAC1_BASE + 0x0bc)||316|
DMAC1_CTL4_1|dg|#define DMAC1_CTL4_1((DMAC1_BASE + 0x0bd)||317|
DMAC1_CTL4_2|dg|#define DMAC1_CTL4_2((DMAC1_BASE + 0x0be)||318|
DMAC1_CTL4|dg|#define DMAC1_CTL4((DMAC1_BASE + 0x0bc)||315|
DMAC1_CTL5_0|dg|#define DMAC1_CTL5_0((DMAC1_BASE + 0x0e8)||334|
DMAC1_CTL5_1|dg|#define DMAC1_CTL5_1((DMAC1_BASE + 0x0e9)||335|
DMAC1_CTL5_2|dg|#define DMAC1_CTL5_2((DMAC1_BASE + 0x0ea)||336|
DMAC1_CTL5|dg|#define DMAC1_CTL5((DMAC1_BASE + 0x0e8)||333|
DMAC1_DAR0|dg|#define DMAC1_DAR0((DMAC1_BASE + 0x004)||241|
DMAC1_DAR1|dg|#define DMAC1_DAR1((DMAC1_BASE + 0x030)||259|
DMAC1_DAR2|dg|#define DMAC1_DAR2((DMAC1_BASE + 0x05c)||277|
DMAC1_DAR3|dg|#define DMAC1_DAR3((DMAC1_BASE + 0x088)||295|
DMAC1_DAR4|dg|#define DMAC1_DAR4((DMAC1_BASE + 0x0b4)||313|
DMAC1_DAR5|dg|#define DMAC1_DAR5((DMAC1_BASE + 0x0e0)||331|
DMAC1_DMACFGREG|dg|#define DMAC1_DMACFGREG((DMAC1_BASE + 0x1cc)||380|
DMAC1_DSR0_H|dg|#define DMAC1_DSR0_H((DMAC1_BASE + 0x029)||256|
DMAC1_DSR0_L|dg|#define DMAC1_DSR0_L((DMAC1_BASE + 0x028)||255|
DMAC1_DSR0|dg|#define DMAC1_DSR0((DMAC1_BASE + 0x028)||254|
DMAC1_DSR1_H|dg|#define DMAC1_DSR1_H((DMAC1_BASE + 0x055)||274|
DMAC1_DSR1_L|dg|#define DMAC1_DSR1_L((DMAC1_BASE + 0x054)||273|
DMAC1_DSR1|dg|#define DMAC1_DSR1((DMAC1_BASE + 0x054)||272|
DMAC1_DSR2_H|dg|#define DMAC1_DSR2_H((DMAC1_BASE + 0x081)||292|
DMAC1_DSR2_L|dg|#define DMAC1_DSR2_L((DMAC1_BASE + 0x080)||291|
DMAC1_DSR2|dg|#define DMAC1_DSR2((DMAC1_BASE + 0x080)||290|
DMAC1_DSR3_H|dg|#define DMAC1_DSR3_H((DMAC1_BASE + 0x0ad)||310|
DMAC1_DSR3_L|dg|#define DMAC1_DSR3_L((DMAC1_BASE + 0x0ac)||309|
DMAC1_DSR3|dg|#define DMAC1_DSR3((DMAC1_BASE + 0x0ac)||308|
DMAC1_DSR4_H|dg|#define DMAC1_DSR4_H((DMAC1_BASE + 0x0d9)||328|
DMAC1_DSR4_L|dg|#define DMAC1_DSR4_L((DMAC1_BASE + 0x0d8)||327|
DMAC1_DSR4|dg|#define DMAC1_DSR4((DMAC1_BASE + 0x0d8)||326|
DMAC1_DSR5_H|dg|#define DMAC1_DSR5_H((DMAC1_BASE + 0x105)||346|
DMAC1_DSR5_L|dg|#define DMAC1_DSR5_L((DMAC1_BASE + 0x104)||345|
DMAC1_DSR5|dg|#define DMAC1_DSR5((DMAC1_BASE + 0x104)||344|
DMAC1_ENBLOCK|dg|#define DMAC1_ENBLOCK((DMAC1_BASE + 0x18c)||362|
DMAC1_ENDSTTRAN|dg|#define DMAC1_ENDSTTRAN((DMAC1_BASE + 0x194)||364|
DMAC1_ENERR|dg|#define DMAC1_ENERR((DMAC1_BASE + 0x198)||365|
DMAC1_ENSRCTRAN|dg|#define DMAC1_ENSRCTRAN((DMAC1_BASE + 0x190)||363|
DMAC1_ENTFR|dg|#define DMAC1_ENTFR((DMAC1_BASE + 0x188)||361|
DMAC1_LLP0|dg|#define DMAC1_LLP0((DMAC1_BASE + 0x008)||242|
DMAC1_LLP1|dg|#define DMAC1_LLP1((DMAC1_BASE + 0x034)||260|
DMAC1_LLP2|dg|#define DMAC1_LLP2((DMAC1_BASE + 0x060)||278|
DMAC1_LLP3|dg|#define DMAC1_LLP3((DMAC1_BASE + 0x08c)||296|
DMAC1_LLP4|dg|#define DMAC1_LLP4((DMAC1_BASE + 0x0b8)||314|
DMAC1_LLP5|dg|#define DMAC1_LLP5((DMAC1_BASE + 0x0e4)||332|
DMAC1_MAXCHANNEL|dg|#define DMAC1_MAXCHANNEL||487|
DMAC1_RAWBLOCK|dg|#define DMAC1_RAWBLOCK((DMAC1_BASE + 0x164)||350|
DMAC1_RAWDSTTRAN|dg|#define DMAC1_RAWDSTTRAN((DMAC1_BASE + 0x16c)||352|
DMAC1_RAWERR|dg|#define DMAC1_RAWERR((DMAC1_BASE + 0x170)||353|
DMAC1_RAWSRCTRAN|dg|#define DMAC1_RAWSRCTRAN((DMAC1_BASE + 0x168)||351|
DMAC1_RAWTFR|dg|#define DMAC1_RAWTFR((DMAC1_BASE + 0x160)||349|
DMAC1_REQDSTREG|dg|#define DMAC1_REQDSTREG((DMAC1_BASE + 0x1b8)||376|
DMAC1_REQSRCREG|dg|#define DMAC1_REQSRCREG((DMAC1_BASE + 0x1b4)||375|
DMAC1_SAR0|dg|#define DMAC1_SAR0((DMAC1_BASE + 0x000)||240|
DMAC1_SAR1|dg|#define DMAC1_SAR1((DMAC1_BASE + 0x02c)||258|
DMAC1_SAR2|dg|#define DMAC1_SAR2((DMAC1_BASE + 0x058)||276|
DMAC1_SAR3|dg|#define DMAC1_SAR3((DMAC1_BASE + 0x084)||294|
DMAC1_SAR4|dg|#define DMAC1_SAR4((DMAC1_BASE + 0x0b0)||312|
DMAC1_SAR5|dg|#define DMAC1_SAR5((DMAC1_BASE + 0x0dc)||330|
DMAC1_SGLREQDSTREG|dg|#define DMAC1_SGLREQDSTREG((DMAC1_BASE + 0x1c0)||378|
DMAC1_SGLREQSRCREG|dg|#define DMAC1_SGLREQSRCREG((DMAC1_BASE + 0x1bc)||377|
DMAC1_SGR0_H|dg|#define DMAC1_SGR0_H((DMAC1_BASE + 0x026)||253|
DMAC1_SGR0_L|dg|#define DMAC1_SGR0_L((DMAC1_BASE + 0x025)||252|
DMAC1_SGR0|dg|#define DMAC1_SGR0((DMAC1_BASE + 0x024)||251|
DMAC1_SGR1_H|dg|#define DMAC1_SGR1_H((DMAC1_BASE + 0x051)||271|
DMAC1_SGR1_L|dg|#define DMAC1_SGR1_L((DMAC1_BASE + 0x050)||270|
DMAC1_SGR1|dg|#define DMAC1_SGR1((DMAC1_BASE + 0x050)||269|
DMAC1_SGR2_H|dg|#define DMAC1_SGR2_H((DMAC1_BASE + 0x07d)||289|
DMAC1_SGR2_L|dg|#define DMAC1_SGR2_L((DMAC1_BASE + 0x07c)||288|
DMAC1_SGR2|dg|#define DMAC1_SGR2((DMAC1_BASE + 0x07c)||287|
DMAC1_SGR3_H|dg|#define DMAC1_SGR3_H((DMAC1_BASE + 0x0a9)||307|
DMAC1_SGR3_L|dg|#define DMAC1_SGR3_L((DMAC1_BASE + 0x0a8)||306|
DMAC1_SGR3|dg|#define DMAC1_SGR3((DMAC1_BASE + 0x0a8)||305|
DMAC1_SGR4_H|dg|#define DMAC1_SGR4_H((DMAC1_BASE + 0x0d5)||325|
DMAC1_SGR4_L|dg|#define DMAC1_SGR4_L((DMAC1_BASE + 0x0d4)||324|
DMAC1_SGR4|dg|#define DMAC1_SGR4((DMAC1_BASE + 0x0d4)||323|
DMAC1_SGR5_H|dg|#define DMAC1_SGR5_H((DMAC1_BASE + 0x101)||343|
DMAC1_SGR5_L|dg|#define DMAC1_SGR5_L((DMAC1_BASE + 0x100)||342|
DMAC1_SGR5|dg|#define DMAC1_SGR5((DMAC1_BASE + 0x100)||341|
DMAC1_STATUSBLOCK|dg|#define DMAC1_STATUSBLOCK((DMAC1_BASE + 0x178)||356|
DMAC1_STATUSDSTTRAN|dg|#define DMAC1_STATUSDSTTRAN((DMAC1_BASE + 0x180)||358|
DMAC1_STATUSERR|dg|#define DMAC1_STATUSERR((DMAC1_BASE + 0x184)||359|
DMAC1_STATUSINT|dg|#define DMAC1_STATUSINT((DMAC1_BASE + 0x1b0)||373|
DMAC1_STATUSSRCTRAN|dg|#define DMAC1_STATUSSRCTRAN((DMAC1_BASE + 0x17c)||357|
DMAC1_STATUSTFR|dg|#define DMAC1_STATUSTFR((DMAC1_BASE + 0x174)||355|
DMAC_BLOCK_INT|dg|#define DMAC_BLOCK_INT||480|
DMAC_CFG_0_CH_PRIORBF|dg|#define DMAC_CFG_0_CH_PRIORBF||463|
DMAC_CFG_0_CH_PRIOR_0|dg|#define DMAC_CFG_0_CH_PRIOR_0||464|
DMAC_CFG_0_CH_PRIOR_1|dg|#define DMAC_CFG_0_CH_PRIOR_1||465|
DMAC_CFG_0_CH_PRIOR_2|dg|#define DMAC_CFG_0_CH_PRIOR_2||466|
DMAC_CFG_0_CH_PRIOR_3|dg|#define DMAC_CFG_0_CH_PRIOR_3||467|
DMAC_CFG_0_CH_PRIOR_4|dg|#define DMAC_CFG_0_CH_PRIOR_4||468|
DMAC_CFG_0_CH_PRIOR_5|dg|#define DMAC_CFG_0_CH_PRIOR_5||469|
DMAC_CFG_0_CH_PRIOR_6|dg|#define DMAC_CFG_0_CH_PRIOR_6||470|
DMAC_CFG_0_CH_PRIOR_7|dg|#define DMAC_CFG_0_CH_PRIOR_7||471|
DMAC_CFG_0_CH_SUSPB|dg|#define DMAC_CFG_0_CH_SUSPB||461|
DMAC_CFG_0_FIFO_EMPTYB|dg|#define DMAC_CFG_0_FIFO_EMPTYB||460|
DMAC_CFG_0_HS_SEL_DSTB|dg|#define DMAC_CFG_0_HS_SEL_DSTB||456|
DMAC_CFG_0_HS_SEL_DST_HARD|dg|#define DMAC_CFG_0_HS_SEL_DST_HARD||458|
DMAC_CFG_0_HS_SEL_DST_SOFT|dg|#define DMAC_CFG_0_HS_SEL_DST_SOFT||457|
DMAC_CFG_0_HS_SEL_SRCB|dg|#define DMAC_CFG_0_HS_SEL_SRCB||452|
DMAC_CFG_0_HS_SEL_SRC_HARD|dg|#define DMAC_CFG_0_HS_SEL_SRC_HARD||454|
DMAC_CFG_0_HS_SEL_SRC_SOFT|dg|#define DMAC_CFG_0_HS_SEL_SRC_SOFT||453|
DMAC_CFG_1_RELOAD_DSTB|dg|#define DMAC_CFG_1_RELOAD_DSTB||449|
DMAC_CFG_1_RELOAD_SRCB|dg|#define DMAC_CFG_1_RELOAD_SRCB||450|
DMAC_CFG_2_DEST_PERBF|dg|#define DMAC_CFG_2_DEST_PERBF||434|