dtt6c03b_zsp0_h.lex

此源码是基于大唐微电子的DSP芯片ZSP的串口程序

#DTT6C03B_ZSP0.h
CAMIF_BASE|dg|#define CAMIF_BASE||42|
CH0|dg|#define CH0||816|
CH10|dg|#define CH10||826|
CH11|dg|#define CH11||827|
CH12|dg|#define CH12||828|
CH13|dg|#define CH13||829|
CH14|dg|#define CH14||830|
CH15|dg|#define CH15||831|
CH1|dg|#define CH1||817|
CH2|dg|#define CH2||818|
CH3|dg|#define CH3||819|
CH4|dg|#define CH4||820|
CH5|dg|#define CH5||821|
CH6|dg|#define CH6||822|
CH7|dg|#define CH7||823|
CH8|dg|#define CH8||824|
CH9|dg|#define CH9||825|
CHDEC_BASE|dg|#define CHDEC_BASE||25|
CPR_BASE|dg|#define CPR_BASE||51|
CTLMS_ARM2ZSP0_INT_ARM|dg|#define CTLMS_ARM2ZSP0_INT_ARM((CTLMS_ARM_BASE + 0x000)||1190|
CTLMS_ARM2ZSP0_INT_ZSP|dg|#define CTLMS_ARM2ZSP0_INT_ZSP((CTLMS_ZSP_BASE + 0x000)||1215|
CTLMS_ARM2ZSP1_INT_ARM|dg|#define CTLMS_ARM2ZSP1_INT_ARM((CTLMS_ARM_BASE + 0x002)||1191|
CTLMS_ARM2ZSP1_INT_ZSP|dg|#define CTLMS_ARM2ZSP1_INT_ZSP((CTLMS_ZSP_BASE + 0x002)||1216|
CTLMS_ARM_BASE|dg|#define CTLMS_ARM_BASE||30|
CTLMS_DMAC0_ZSP0_INT_EN|dg|#define CTLMS_DMAC0_ZSP0_INT_EN((CTLMS_ZSP_BASE + 0x018)||1229|
CTLMS_DMAC0_ZSP1_INT_EN|dg|#define CTLMS_DMAC0_ZSP1_INT_EN((CTLMS_ZSP_BASE + 0x01a)||1230|
CTLMS_DMAC1_ZSP0_INT_EN|dg|#define CTLMS_DMAC1_ZSP0_INT_EN((CTLMS_ZSP_BASE + 0x010)||1227|
CTLMS_DMAC1_ZSP1_INT_EN|dg|#define CTLMS_DMAC1_ZSP1_INT_EN((CTLMS_ZSP_BASE + 0x012)||1228|
CTLMS_DPRAM|dg|#define CTLMS_DPRAM((CTLMS_ZSP_BASE + 0x800)||1235|
CTLMS_GPIO1_ZSP0_INT_EN_H|dg|#define CTLMS_GPIO1_ZSP0_INT_EN_H((CTLMS_ZSP_BASE + 0x00d)||1223|
CTLMS_GPIO1_ZSP0_INT_EN_L|dg|#define CTLMS_GPIO1_ZSP0_INT_EN_L((CTLMS_ZSP_BASE + 0x00c)||1222|
CTLMS_GPIO1_ZSP0_INT_EN|dg|#define CTLMS_GPIO1_ZSP0_INT_EN((CTLMS_ZSP_BASE + 0x00c)||1221|
CTLMS_GPIO1_ZSP1_INT_EN_H|dg|#define CTLMS_GPIO1_ZSP1_INT_EN_H((CTLMS_ZSP_BASE + 0x00f)||1226|
CTLMS_GPIO1_ZSP1_INT_EN_L|dg|#define CTLMS_GPIO1_ZSP1_INT_EN_L((CTLMS_ZSP_BASE + 0x00e)||1225|
CTLMS_GPIO1_ZSP1_INT_EN|dg|#define CTLMS_GPIO1_ZSP1_INT_EN((CTLMS_ZSP_BASE + 0x00e)||1224|
CTLMS_MODE_SEL|dg|#define CTLMS_MODE_SEL((CTLMS_ARM_BASE + 0x26)||1208|
CTLMS_MUX0_HIGH|dg|#define CTLMS_MUX0_HIGH((CTLMS_ARM_BASE + 0x016)||1206|
CTLMS_MUX0_LOW_H|dg|#define CTLMS_MUX0_LOW_H((CTLMS_ARM_BASE + 0x015)||1205|
CTLMS_MUX0_LOW_L|dg|#define CTLMS_MUX0_LOW_L((CTLMS_ARM_BASE + 0x014)||1204|
CTLMS_MUX0_LOW|dg|#define CTLMS_MUX0_LOW((CTLMS_ARM_BASE + 0x014)||1203|
CTLMS_MUX1_HIGH_H|dg|#define CTLMS_MUX1_HIGH_H((CTLMS_ARM_BASE + 0x013)||1202|
CTLMS_MUX1_HIGH_L|dg|#define CTLMS_MUX1_HIGH_L((CTLMS_ARM_BASE + 0x012)||1201|
CTLMS_MUX1_HIGH|dg|#define CTLMS_MUX1_HIGH((CTLMS_ARM_BASE + 0x012)||1200|
CTLMS_MUX1_LOW_H|dg|#define CTLMS_MUX1_LOW_H((CTLMS_ARM_BASE + 0x011)||1199|
CTLMS_MUX1_LOW_L|dg|#define CTLMS_MUX1_LOW_L((CTLMS_ARM_BASE + 0x010)||1198|
CTLMS_MUX1_LOW|dg|#define CTLMS_MUX1_LOW((CTLMS_ARM_BASE + 0x010)||1197|
CTLMS_MUX_MIS|dg|#define CTLMS_MUX_MIS((CTLMS_ARM_BASE + 0x00E)||1196|
CTLMS_OUTPUT_CTRL|dg|#define CTLMS_OUTPUT_CTRL((CTLMS_ARM_BASE + 0x018)||1207|
CTLMS_ZSP02ARM_INT_ARM|dg|#define CTLMS_ZSP02ARM_INT_ARM((CTLMS_ARM_BASE + 0x004)||1192|
CTLMS_ZSP02ARM_INT_ZSP|dg|#define CTLMS_ZSP02ARM_INT_ZSP((CTLMS_ZSP_BASE + 0x004)||1217|
CTLMS_ZSP02ZSP1_INT_ARM|dg|#define CTLMS_ZSP02ZSP1_INT_ARM((CTLMS_ARM_BASE + 0x006)||1193|
CTLMS_ZSP02ZSP1_INT_ZSP|dg|#define CTLMS_ZSP02ZSP1_INT_ZSP((CTLMS_ZSP_BASE + 0x006)||1218|
CTLMS_ZSP0_CTRL_H|dg|#define CTLMS_ZSP0_CTRL_H((CTLMS_ARM_BASE + 0x29)||1210|
CTLMS_ZSP0_CTRL_L|dg|#define CTLMS_ZSP0_CTRL_L((CTLMS_ARM_BASE + 0x28)||1209|
CTLMS_ZSP0_INT13_EN|dg|#define CTLMS_ZSP0_INT13_EN((CTLMS_ZSP_BASE + 0x020)||1231|
CTLMS_ZSP12ARM_INT_ARM|dg|#define CTLMS_ZSP12ARM_INT_ARM((CTLMS_ARM_BASE + 0x008)||1194|
CTLMS_ZSP12ARM_INT_ZSP|dg|#define CTLMS_ZSP12ARM_INT_ZSP((CTLMS_ZSP_BASE + 0x008)||1219|
CTLMS_ZSP12ZSP0_INT_ARM|dg|#define CTLMS_ZSP12ZSP0_INT_ARM((CTLMS_ARM_BASE + 0x00a)||1195|
CTLMS_ZSP12ZSP0_INT_ZSP|dg|#define CTLMS_ZSP12ZSP0_INT_ZSP((CTLMS_ZSP_BASE + 0x00a)||1220|
CTLMS_ZSP1_CTRL_H|dg|#define CTLMS_ZSP1_CTRL_H((CTLMS_ARM_BASE + 0x2B)||1212|
CTLMS_ZSP1_CTRL_L|dg|#define CTLMS_ZSP1_CTRL_L((CTLMS_ARM_BASE + 0x2A)||1211|
CTLMS_ZSP1_INT0_EN|dg|#define CTLMS_ZSP1_INT0_EN((CTLMS_ZSP_BASE + 0x022)||1232|
CTLMS_ZSP1_INT12_EN|dg|#define CTLMS_ZSP1_INT12_EN((CTLMS_ZSP_BASE + 0x024)||1233|
CTLMS_ZSP_BASE|dg|#define CTLMS_ZSP_BASE||29|
CTLMS_ZSP_INT_ST|dg|#define CTLMS_ZSP_INT_ST((CTLMS_ZSP_BASE + 0x026)||1234|
DMAC0_BASE|dg|#define DMAC0_BASE||40|
DMAC0_CFG0_0|dg|#define DMAC0_CFG0_0((DMAC0_BASE + 0x020)||66|
DMAC0_CFG0_1|dg|#define DMAC0_CFG0_1((DMAC0_BASE + 0x021)||67|
DMAC0_CFG0_2|dg|#define DMAC0_CFG0_2((DMAC0_BASE + 0x022)||68|
DMAC0_CFG0|dg|#define DMAC0_CFG0((DMAC0_BASE + 0x020)||65|
DMAC0_CFG1_0|dg|#define DMAC0_CFG1_0((DMAC0_BASE + 0x04c)||84|
DMAC0_CFG1_1|dg|#define DMAC0_CFG1_1((DMAC0_BASE + 0x04d)||85|
DMAC0_CFG1_2|dg|#define DMAC0_CFG1_2((DMAC0_BASE + 0x04e)||86|
DMAC0_CFG1|dg|#define DMAC0_CFG1((DMAC0_BASE + 0x04c)||83|
DMAC0_CFG2_0|dg|#define DMAC0_CFG2_0((DMAC0_BASE + 0x078)||102|
DMAC0_CFG2_1|dg|#define DMAC0_CFG2_1((DMAC0_BASE + 0x079)||103|
DMAC0_CFG2_2|dg|#define DMAC0_CFG2_2((DMAC0_BASE + 0x07a)||104|
DMAC0_CFG2|dg|#define DMAC0_CFG2((DMAC0_BASE + 0x078)||101|
DMAC0_CFG3_0|dg|#define DMAC0_CFG3_0((DMAC0_BASE + 0x0a4)||120|
DMAC0_CFG3_1|dg|#define DMAC0_CFG3_1((DMAC0_BASE + 0x0a5)||121|
DMAC0_CFG3_2|dg|#define DMAC0_CFG3_2((DMAC0_BASE + 0x0a6)||122|
DMAC0_CFG3|dg|#define DMAC0_CFG3((DMAC0_BASE + 0x0a4)||119|
DMAC0_CFG4_0|dg|#define DMAC0_CFG4_0((DMAC0_BASE + 0x0d0)||138|
DMAC0_CFG4_1|dg|#define DMAC0_CFG4_1((DMAC0_BASE + 0x0d1)||139|
DMAC0_CFG4_2|dg|#define DMAC0_CFG4_2((DMAC0_BASE + 0x0d2)||140|
DMAC0_CFG4|dg|#define DMAC0_CFG4((DMAC0_BASE + 0x0d0)||137|
DMAC0_CFG5_0|dg|#define DMAC0_CFG5_0((DMAC0_BASE + 0x0fc)||156|
DMAC0_CFG5_1|dg|#define DMAC0_CFG5_1((DMAC0_BASE + 0x0fd)||157|
DMAC0_CFG5_2|dg|#define DMAC0_CFG5_2((DMAC0_BASE + 0x0fe)||158|
DMAC0_CFG5|dg|#define DMAC0_CFG5((DMAC0_BASE + 0x0fc)||155|
DMAC0_CFG6_0|dg|#define DMAC0_CFG6_0((DMAC0_BASE + 0x128)||174|
DMAC0_CFG6_1|dg|#define DMAC0_CFG6_1((DMAC0_BASE + 0x129)||175|
DMAC0_CFG6_2|dg|#define DMAC0_CFG6_2((DMAC0_BASE + 0x12a)||176|
DMAC0_CFG6|dg|#define DMAC0_CFG6((DMAC0_BASE + 0x128)||173|
DMAC0_CFG7_0|dg|#define DMAC0_CFG7_0((DMAC0_BASE + 0x154)||192|
DMAC0_CFG7_1|dg|#define DMAC0_CFG7_1((DMAC0_BASE + 0x155)||193|
DMAC0_CFG7_2|dg|#define DMAC0_CFG7_2((DMAC0_BASE + 0x156)||194|
DMAC0_CFG7|dg|#define DMAC0_CFG7((DMAC0_BASE + 0x154)||191|
DMAC0_CHENREG|dg|#define DMAC0_CHENREG((DMAC0_BASE + 0x1d0)||234|
DMAC0_CLEARBLOCK|dg|#define DMAC0_CLEARBLOCK((DMAC0_BASE + 0x1a0)||221|
DMAC0_CLEARDSTTRAN|dg|#define DMAC0_CLEARDSTTRAN((DMAC0_BASE + 0x1a8)||223|
DMAC0_CLEARERR|dg|#define DMAC0_CLEARERR((DMAC0_BASE + 0x1ac)||224|
DMAC0_CLEARSRCTRAN|dg|#define DMAC0_CLEARSRCTRAN((DMAC0_BASE + 0x1a4)||222|
DMAC0_CLEARTFR|dg|#define DMAC0_CLEARTFR((DMAC0_BASE + 0x19c)||220|
DMAC0_CTL0_0|dg|#define DMAC0_CTL0_0((DMAC0_BASE + 0x00c)||62|
DMAC0_CTL0_1|dg|#define DMAC0_CTL0_1((DMAC0_BASE + 0x00d)||63|
DMAC0_CTL0_2|dg|#define DMAC0_CTL0_2((DMAC0_BASE + 0x00e)||64|
DMAC0_CTL0|dg|#define DMAC0_CTL0((DMAC0_BASE + 0x00c)||61|
DMAC0_CTL1_0|dg|#define DMAC0_CTL1_0((DMAC0_BASE + 0x038)||80|
DMAC0_CTL1_1|dg|#define DMAC0_CTL1_1((DMAC0_BASE + 0x039)||81|
DMAC0_CTL1_2|dg|#define DMAC0_CTL1_2((DMAC0_BASE + 0x03a)||82|
DMAC0_CTL1|dg|#define DMAC0_CTL1((DMAC0_BASE + 0x038)||79|
DMAC0_CTL2_0|dg|#define DMAC0_CTL2_0((DMAC0_BASE + 0x064)||98|
DMAC0_CTL2_1|dg|#define DMAC0_CTL2_1((DMAC0_BASE + 0x065)||99|
DMAC0_CTL2_2|dg|#define DMAC0_CTL2_2((DMAC0_BASE + 0x066)||100|
DMAC0_CTL2|dg|#define DMAC0_CTL2((DMAC0_BASE + 0x064)||97|
DMAC0_CTL3_0|dg|#define DMAC0_CTL3_0((DMAC0_BASE + 0x090)||116|
DMAC0_CTL3_1|dg|#define DMAC0_CTL3_1((DMAC0_BASE + 0x091)||117|
DMAC0_CTL3_2|dg|#define DMAC0_CTL3_2((DMAC0_BASE + 0x092)||118|
DMAC0_CTL3|dg|#define DMAC0_CTL3((DMAC0_BASE + 0x090)||115|
DMAC0_CTL4_0|dg|#define DMAC0_CTL4_0((DMAC0_BASE + 0x0bc)||134|
DMAC0_CTL4_1|dg|#define DMAC0_CTL4_1((DMAC0_BASE + 0x0bd)||135|
DMAC0_CTL4_2|dg|#define DMAC0_CTL4_2((DMAC0_BASE + 0x0be)||136|
DMAC0_CTL4|dg|#define DMAC0_CTL4((DMAC0_BASE + 0x0bc)||133|
DMAC0_CTL5_0|dg|#define DMAC0_CTL5_0((DMAC0_BASE + 0x0e8)||152|
DMAC0_CTL5_1|dg|#define DMAC0_CTL5_1((DMAC0_BASE + 0x0e9)||153|
DMAC0_CTL5_2|dg|#define DMAC0_CTL5_2((DMAC0_BASE + 0x0ea)||154|
DMAC0_CTL5|dg|#define DMAC0_CTL5((DMAC0_BASE + 0x0e8)||151|
DMAC0_CTL6_0|dg|#define DMAC0_CTL6_0((DMAC0_BASE + 0x114)||170|
DMAC0_CTL6_1|dg|#define DMAC0_CTL6_1((DMAC0_BASE + 0x115)||171|
DMAC0_CTL6_2|dg|#define DMAC0_CTL6_2((DMAC0_BASE + 0x116)||172|
DMAC0_CTL6|dg|#define DMAC0_CTL6((DMAC0_BASE + 0x114)||169|
DMAC0_CTL7_0|dg|#define DMAC0_CTL7_0((DMAC0_BASE + 0x140)||188|
DMAC0_CTL7_1|dg|#define DMAC0_CTL7_1((DMAC0_BASE + 0x141)||189|
DMAC0_CTL7_2|dg|#define DMAC0_CTL7_2((DMAC0_BASE + 0x142)||190|
DMAC0_CTL7|dg|#define DMAC0_CTL7((DMAC0_BASE + 0x140)||187|
DMAC0_DAR0|dg|#define DMAC0_DAR0((DMAC0_BASE + 0x004)||59|
DMAC0_DAR1|dg|#define DMAC0_DAR1((DMAC0_BASE + 0x030)||77|
DMAC0_DAR2|dg|#define DMAC0_DAR2((DMAC0_BASE + 0x05c)||95|
DMAC0_DAR3|dg|#define DMAC0_DAR3((DMAC0_BASE + 0x088)||113|
DMAC0_DAR4|dg|#define DMAC0_DAR4((DMAC0_BASE + 0x0b4)||131|
DMAC0_DAR5|dg|#define DMAC0_DAR5((DMAC0_BASE + 0x0e0)||149|
DMAC0_DAR6|dg|#define DMAC0_DAR6((DMAC0_BASE + 0x10c)||167|
DMAC0_DAR7|dg|#define DMAC0_DAR7((DMAC0_BASE + 0x138)||185|
DMAC0_DMACFGREG|dg|#define DMAC0_DMACFGREG((DMAC0_BASE + 0x1cc)||233|
DMAC0_DSR0_H|dg|#define DMAC0_DSR0_H((DMAC0_BASE + 0x029)||74|
DMAC0_DSR0_L|dg|#define DMAC0_DSR0_L((DMAC0_BASE + 0x028)||73|
DMAC0_DSR0|dg|#define DMAC0_DSR0((DMAC0_BASE + 0x028)||72|
DMAC0_DSR1_H|dg|#define DMAC0_DSR1_H((DMAC0_BASE + 0x055)||92|
DMAC0_DSR1_L|dg|#define DMAC0_DSR1_L((DMAC0_BASE + 0x054)||91|
DMAC0_DSR1|dg|#define DMAC0_DSR1((DMAC0_BASE + 0x054)||90|
DMAC0_DSR2_H|dg|#define DMAC0_DSR2_H((DMAC0_BASE + 0x081)||110|
DMAC0_DSR2_L|dg|#define DMAC0_DSR2_L((DMAC0_BASE + 0x080)||109|
DMAC0_DSR2|dg|#define DMAC0_DSR2((DMAC0_BASE + 0x080)||108|
DMAC0_DSR3_H|dg|#define DMAC0_DSR3_H((DMAC0_BASE + 0x0ad)||128|
DMAC0_DSR3_L|dg|#define DMAC0_DSR3_L((DMAC0_BASE + 0x0ac)||127|
DMAC0_DSR3|dg|#define DMAC0_DSR3((DMAC0_BASE + 0x0ac)||126|
DMAC0_DSR4_H|dg|#define DMAC0_DSR4_H((DMAC0_BASE + 0x0d9)||146|
DMAC0_DSR4_L|dg|#define DMAC0_DSR4_L((DMAC0_BASE + 0x0d8)||145|
DMAC0_DSR4|dg|#define DMAC0_DSR4((DMAC0_BASE + 0x0d8)||144|
DMAC0_DSR5_H|dg|#define DMAC0_DSR5_H((DMAC0_BASE + 0x105)||164|
DMAC0_DSR5_L|dg|#define DMAC0_DSR5_L((DMAC0_BASE + 0x104)||163|
DMAC0_DSR5|dg|#define DMAC0_DSR5((DMAC0_BASE + 0x104)||162|
DMAC0_DSR6_H|dg|#define DMAC0_DSR6_H((DMAC0_BASE + 0x131)||182|
DMAC0_DSR6_L|dg|#define DMAC0_DSR6_L((DMAC0_BASE + 0x130)||181|
DMAC0_DSR6|dg|#define DMAC0_DSR6((DMAC0_BASE + 0x130)||180|
DMAC0_DSR7_H|dg|#define DMAC0_DSR7_H((DMAC0_BASE + 0x15d)||200|
DMAC0_DSR7_L|dg|#define DMAC0_DSR7_L((DMAC0_BASE + 0x15c)||199|
DMAC0_DSR7|dg|#define DMAC0_DSR7((DMAC0_BASE + 0x15c)||198|
DMAC0_ENBLOCK|dg|#define DMAC0_ENBLOCK((DMAC0_BASE + 0x18c)||215|
DMAC0_ENDSTTRAN|dg|#define DMAC0_ENDSTTRAN((DMAC0_BASE + 0x194)||217|
DMAC0_ENERR|dg|#define DMAC0_ENERR((DMAC0_BASE + 0x198)||218|
DMAC0_ENSRCTRAN|dg|#define DMAC0_ENSRCTRAN((DMAC0_BASE + 0x190)||216|
DMAC0_ENTFR|dg|#define DMAC0_ENTFR((DMAC0_BASE + 0x188)||214|
DMAC0_LLP0|dg|#define DMAC0_LLP0((DMAC0_BASE + 0x008)||60|
DMAC0_LLP1|dg|#define DMAC0_LLP1((DMAC0_BASE + 0x034)||78|
DMAC0_LLP2|dg|#define DMAC0_LLP2((DMAC0_BASE + 0x060)||96|
DMAC0_LLP3|dg|#define DMAC0_LLP3((DMAC0_BASE + 0x08c)||114|
DMAC0_LLP4|dg|#define DMAC0_LLP4((DMAC0_BASE + 0x0b8)||132|
DMAC0_LLP5|dg|#define DMAC0_LLP5((DMAC0_BASE + 0x0e4)||150|
DMAC0_LLP6|dg|#define DMAC0_LLP6((DMAC0_BASE + 0x110)||168|
DMAC0_LLP7|dg|#define DMAC0_LLP7((DMAC0_BASE + 0x13c)||186|
DMAC0_MAXCHANNEL|dg|#define DMAC0_MAXCHANNEL||486|
DMAC0_RAWBLOCK|dg|#define DMAC0_RAWBLOCK((DMAC0_BASE + 0x164)||203|
DMAC0_RAWDSTTRAN|dg|#define DMAC0_RAWDSTTRAN((DMAC0_BASE + 0x16c)||205|
DMAC0_RAWERR|dg|#define DMAC0_RAWERR((DMAC0_BASE + 0x170)||206|
DMAC0_RAWSRCTRAN|dg|#define DMAC0_RAWSRCTRAN((DMAC0_BASE + 0x168)||204|
DMAC0_RAWTFR|dg|#define DMAC0_RAWTFR((DMAC0_BASE + 0x160)||202|
DMAC0_REQDSTREG|dg|#define DMAC0_REQDSTREG((DMAC0_BASE + 0x1b8)||229|
DMAC0_REQSRCREG|dg|#define DMAC0_REQSRCREG((DMAC0_BASE + 0x1b4)||228|
DMAC0_SAR0|dg|#define DMAC0_SAR0((DMAC0_BASE + 0x000)||58|
DMAC0_SAR1|dg|#define DMAC0_SAR1((DMAC0_BASE + 0x02c)||76|
DMAC0_SAR2|dg|#define DMAC0_SAR2((DMAC0_BASE + 0x058)||94|
DMAC0_SAR3|dg|#define DMAC0_SAR3((DMAC0_BASE + 0x084)||112|
DMAC0_SAR4|dg|#define DMAC0_SAR4((DMAC0_BASE + 0x0b0)||130|
DMAC0_SAR5|dg|#define DMAC0_SAR5((DMAC0_BASE + 0x0dc)||148|