📄 m511.rpt
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Device-Specific Information: d:\so2006\cpld-pro\prog+max2\m511\m511.rpt
m511
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'G':
Logic cells placed in LAB 'G'
+----------- LC97 pn_out
| +--------- LC107 M_shift6
| | +------- LC106 M_shift4
| | | +----- LC105 M_shift3
| | | | +--- LC104 M_shift2
| | | | | +- LC100 M_shift1
| | | | | |
| | | | | | Other LABs fed by signals
| | | | | | that feed LAB 'G'
LC | | | | | | | A B C D E F G H | Logic cells that feed LAB 'G':
LC105-> - - * - - - | - - - - - - * - | <-- M_shift3
LC104-> - - - * - - | - - - - - - * - | <-- M_shift2
LC100-> - - - - * - | - - - - - - * - | <-- M_shift1
Pin
83 -> - - - - - - | - - - - - - - - | <-- clk
12 -> * * * * * * | - - - - - - * * | <-- reset
LC128-> * - - - - - | - - - - - - * - | <-- M_shift9
LC126-> - * - - - - | - - - - - - * - | <-- M_shift5
LC124-> - - - - - * | - - - - - - * - | <-- M_shift0
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\so2006\cpld-pro\prog+max2\m511\m511.rpt
m511
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'H':
Logic cells placed in LAB 'H'
+------------------------------- LC123 m_out
| +----------------------------- LC119 m4
| | +--------------------------- LC118 m9
| | | +------------------------- LC117 m1
| | | | +----------------------- LC116 m2
| | | | | +--------------------- LC115 m3
| | | | | | +------------------- LC114 m5
| | | | | | | +----------------- LC113 m6
| | | | | | | | +--------------- LC120 m7
| | | | | | | | | +------------- LC121 m8
| | | | | | | | | | +----------- LC128 M_shift9
| | | | | | | | | | | +--------- LC125 M_shift8
| | | | | | | | | | | | +------- LC127 M_shift7
| | | | | | | | | | | | | +----- LC126 M_shift5
| | | | | | | | | | | | | | +--- LC124 M_shift0
| | | | | | | | | | | | | | | +- LC122 M_factor4
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'H'
LC | | | | | | | | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'H':
LC119-> - - - * - - * - - - - - - - - - | - - - - - - - * | <-- m4
LC118-> * - - * - - - - - - - - - - - - | - - - - - - - * | <-- m9
LC117-> - - - * * - - - - - - - - - - - | - - - - - - - * | <-- m1
LC116-> - - - * - * - - - - - - - - - - | - - - - - - - * | <-- m2
LC115-> - * - * - - - - - - - - - - - - | - - - - - - - * | <-- m3
LC114-> - - - * - - - * - - - - - - - - | - - - - - - - * | <-- m5
LC113-> - - - * - - - - * - - - - - - - | - - - - - - - * | <-- m6
LC120-> - - - * - - - - - * - - - - - - | - - - - - - - * | <-- m7
LC121-> - - * * - - - - - - - - - - - - | - - - - - - - * | <-- m8
LC125-> - - - - - - - - - - * - - * * - | - - - - - - - * | <-- M_shift8
LC127-> - - - - - - - - - - - * - - - - | - - - - - - - * | <-- M_shift7
LC122-> - - - - - - - - - - - - - * - - | - - - - - - - * | <-- M_factor4
Pin
83 -> - - - - - - - - - - - - - - - - | - - - - - - - - | <-- clk
12 -> - - - - - - - - - - * * * * * * | - - - - - - * * | <-- reset
LC107-> - - - - - - - - - - - - * - - - | - - - - - - - * | <-- M_shift6
LC106-> - - - - - - - - - - - - - * - - | - - - - - - - * | <-- M_shift4
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\so2006\cpld-pro\prog+max2\m511\m511.rpt
m511
** EQUATIONS **
clk : INPUT;
reset : INPUT;
-- Node name is ':45' = 'M_factor4'
-- Equation name is 'M_factor4', location is LC122, type is buried.
M_factor4 = DFFE( GND $ VCC, GLOBAL( clk), VCC, VCC, !reset);
-- Node name is 'm_out' = ':2'
-- Equation name is 'm_out', type is output
m_out = DFFE( m9 $ GND, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':37' = 'M_shift0'
-- Equation name is 'M_shift0', location is LC124, type is buried.
M_shift0 = DFFE( M_shift8 $ GND, GLOBAL( clk), VCC, !reset, VCC);
-- Node name is ':36' = 'M_shift1'
-- Equation name is 'M_shift1', location is LC100, type is buried.
M_shift1 = DFFE( M_shift0 $ GND, GLOBAL( clk), !reset, VCC, VCC);
-- Node name is ':35' = 'M_shift2'
-- Equation name is 'M_shift2', location is LC104, type is buried.
M_shift2 = DFFE( M_shift1 $ GND, GLOBAL( clk), !reset, VCC, VCC);
-- Node name is ':34' = 'M_shift3'
-- Equation name is 'M_shift3', location is LC105, type is buried.
M_shift3 = DFFE( M_shift2 $ GND, GLOBAL( clk), !reset, VCC, VCC);
-- Node name is ':33' = 'M_shift4'
-- Equation name is 'M_shift4', location is LC106, type is buried.
M_shift4 = DFFE( M_shift3 $ GND, GLOBAL( clk), !reset, VCC, VCC);
-- Node name is ':32' = 'M_shift5'
-- Equation name is 'M_shift5', location is LC126, type is buried.
M_shift5 = DFFE( M_shift4 $ _EQ001, GLOBAL( clk), !reset, VCC, VCC);
_EQ001 = M_factor4 & M_shift8;
-- Node name is ':31' = 'M_shift6'
-- Equation name is 'M_shift6', location is LC107, type is buried.
M_shift6 = DFFE( M_shift5 $ GND, GLOBAL( clk), !reset, VCC, VCC);
-- Node name is ':30' = 'M_shift7'
-- Equation name is 'M_shift7', location is LC127, type is buried.
M_shift7 = DFFE( M_shift6 $ GND, GLOBAL( clk), !reset, VCC, VCC);
-- Node name is ':29' = 'M_shift8'
-- Equation name is 'M_shift8', location is LC125, type is buried.
M_shift8 = DFFE( M_shift7 $ GND, GLOBAL( clk), !reset, VCC, VCC);
-- Node name is ':28' = 'M_shift9'
-- Equation name is 'M_shift9', location is LC128, type is buried.
M_shift9 = DFFE( M_shift8 $ GND, GLOBAL( clk), !reset, VCC, VCC);
-- Node name is ':21' = 'm1'
-- Equation name is 'm1', location is LC117, type is buried.
m1 = DFFE( _EQ002 $ m4, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = !m1 & !m2 & !m3 & !m4 & !m5 & !m6 & !m7 & !m8 & !m9
# m9;
-- Node name is ':22' = 'm2'
-- Equation name is 'm2', location is LC116, type is buried.
m2 = DFFE( m1 $ GND, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':23' = 'm3'
-- Equation name is 'm3', location is LC115, type is buried.
m3 = DFFE( m2 $ GND, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':19' = 'm4'
-- Equation name is 'm4', location is LC119, type is buried.
m4 = DFFE( m3 $ GND, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':24' = 'm5'
-- Equation name is 'm5', location is LC114, type is buried.
m5 = DFFE( m4 $ GND, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':25' = 'm6'
-- Equation name is 'm6', location is LC113, type is buried.
m6 = DFFE( m5 $ GND, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':26' = 'm7'
-- Equation name is 'm7', location is LC120, type is buried.
m7 = DFFE( m6 $ GND, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':27' = 'm8'
-- Equation name is 'm8', location is LC121, type is buried.
m8 = DFFE( m7 $ GND, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is ':20' = 'm9'
-- Equation name is 'm9', location is LC118, type is buried.
m9 = DFFE( m8 $ GND, GLOBAL( clk), VCC, VCC, VCC);
-- Node name is 'pn_out' = ':16'
-- Equation name is 'pn_out', type is output
pn_out = DFFE( M_shift9 $ GND, GLOBAL( clk), !reset, VCC, VCC);
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information d:\so2006\cpld-pro\prog+max2\m511\m511.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 4,020K
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