m511.vhd

扩频通信M511序列,编码,通用VHDL语言,用于相关

------------------------------------------------------------------2006.12.20
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity m511 is
      port
          ( reset    :in  std_logic;
            m_out :out std_logic;  -- m out
          --  reset :in  std_logic;
            M_switch :in  std_logic_vector(11 downto 0);
            pn_out   :buffer std_logic;  --M sequence output.

            clk   :in  std_logic  -- heigh clock
            --m_out4 :out std_logic;--early
             --m_out5 :out std_logic;--peak
            --m_out6 :out std_logic;  --later
           -- clk4out: out std_logic     --4 times clock
          );
end m511;
--------------------------------
architecture behave of m511 is
--signal m_shift         :std_logic_vector(35 downto 0);
--signal feedback_factor :std_logic_vector(8 downto 1);
--signal clk4: std_logic;
signal m1,m2,m3,m4,m5,m6,m7,m8,m9:std_logic:='0';
signal M_shift           :std_logic_vector(9 downto 0);  --shift register of M sequence.
signal M_factor          :std_logic_vector(11 downto 0); --store M feedback factor.

--signal count1:std_logic_vector(4 downto 0);
--signal c0,c1,c2,c3,c4,c5,c6,c7,c8,c9,c10: std_logic:='0';

begin
--------------------1 process   m seial
     process(clk)
     variable c1:std_logic; 
      begin
     -- if rising_edge(clk) then        --超前/滞后判决
     if(clk'event and clk='1') then
          --m0<=m9;
          c1:=(m4 xor m9)or ( not ( m9 or m1 or m2 or m3 or m4 or m5 or m6 or m7  or m8));
          m1<=c1;
          m2<=m1;
          m3<=m2;
          m4<=m3; 
	      m5<=m4; 
          m6<=m5; 	 
          m7<=m6; 
          m8<=m7;
          m9<=m8;
       	  m_out<=m9;
       end if;
      end process;

--to generate M_sequence and fu_clk. g=1021
M_sequence:process(reset,clk)
           variable c0  :std_logic;     --the first bit of feedback factor c0.
           begin
                if(reset='1') then
                   M_shift<="0000000001";   --setup initial value.
                   pn_out<='0';
                                                                         
                elsif(clk'event and clk='1') then 
                      M_factor<="000000010000";
                      c0:=M_shift(8);--feedback to m0, only  m0 to m8 for m,
                         M_shift(9)<=M_shift(8);                                                                    
                         for i in 8 downto 1 loop                                                 
                             M_shift(i)<=M_shift(i-1) xor (c0 and M_factor(i-1));
                         end loop;
                         M_shift(0)<=c0; --feedback to m0, only  m0 to m8 for m,
                         pn_out<=M_shift(9);--M out m9 for delay 
                    -- end if  ;                                                                       
                end if;                
  end process M_sequence;
end behave;
--all end.
------------