📄 chip1.rpt
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| | +------------------------- LC125 out
| | | +----------------------- LC123 flag
| | | | +--------------------- LC122 n4
| | | | | +------------------- LC121 n3
| | | | | | +----------------- LC120 n2
| | | | | | | +--------------- LC119 n1
| | | | | | | | +------------- LC118 n0
| | | | | | | | | +----------- LC117 c4
| | | | | | | | | | +--------- LC116 ~128~1
| | | | | | | | | | | +------- LC115 c1
| | | | | | | | | | | | +----- LC114 c2
| | | | | | | | | | | | | +--- LC113 c3
| | | | | | | | | | | | | | +- LC127 ~158~1
| | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | that feed LAB 'H'
LC | | | | | | | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'H':
LC126-> - - - - - * - - - - - - - - - | - - - - - - - * | <-- |lpm_add_sub:160|addcore:adder|addcore:adder0|result_node3
LC124-> - - - - - * - - - - - - - - - | - - - - - - - * | <-- |lpm_add_sub:161|addcore:adder|addcore:adder0|result_node3
LC123-> - - - * * * * * * - - - - - - | - - - - - - - * | <-- flag
LC122-> - - - * * * * * * * * * * * * | - - - - - - - * | <-- n4
LC121-> * * - * * * * * * * * * * * * | - - - - - - - * | <-- n3
LC120-> * * - * * * * * * * * * * * * | - - - - - - - * | <-- n2
LC119-> * * - * * * * * * * - * * * * | - - - - - - - * | <-- n1
LC118-> * * - * * * * * * * - * * * * | - - - - - - - * | <-- n0
LC117-> - - * - - - - - - * * * - - - | - - - - - - - * | <-- c4
LC116-> - - - - - - - - - - - * - - - | - - - - - - - * | <-- ~128~1
LC115-> - - - - - - - - - - * * * - - | - - - - - - - * | <-- c1
LC114-> - - - - - - - - - - - - * * - | - - - - - - - * | <-- c2
LC113-> - - - - - - - - - * - - - * - | - - - - - - - * | <-- c3
LC127-> - - * - - - - - - - - - - - - | - - - - - - - * | <-- ~158~1
Pin
83 -> - - - - - - - - - - - - - - - | - - - - - - - - | <-- clk
12 -> - - - * - - - - - * * * * * - | - - - - - - - * | <-- reset
11 -> - - - * * * * * * - - - - - - | - - - - - - - * | <-- t1
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\so2006\cpld-pro\prog+max2\m15\chip1.rpt
chip1
** EQUATIONS **
clk : INPUT;
reset : INPUT;
t1 : INPUT;
-- Node name is ':129' = 'c1'
-- Equation name is 'c1', location is LC115, type is buried.
c1 = DFFE( _EQ001 $ _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = c1 & c4 & !_LC116 & n0 & n1 & n3 & _X001
# !c1 & !c4 & !_LC116 & n0 & n1 & n3 & _X001
# !c1 & !_LC116 & !n1 & !n2 & !n4 & !reset & _X001
# !c1 & !_LC116 & !n0 & !n2 & !n4 & !reset & _X001;
_X001 = EXP(!c1 & !c4 & !reset);
_EQ002 = !_LC116 & _X001;
_X001 = EXP(!c1 & !c4 & !reset);
-- Node name is ':138' = 'c2'
-- Equation name is 'c2', location is LC114, type is buried.
c2 = DFFE( _EQ003 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = c1 & n0 & n1 & !n2 & n3 & !n4
# c2 & !n2 & !n4 & !reset & _X002
# c1 & n2 & n3 & !n4
# c2 & !n3 & !n4 & !reset
# c1 & n4;
_X002 = EXP( n0 & n1);
-- Node name is ':147' = 'c3'
-- Equation name is 'c3', location is LC113, type is buried.
c3 = DFFE( _EQ004 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = c2 & n0 & n1 & !n2 & n3 & !n4
# c3 & !n2 & !n4 & !reset & _X002
# c2 & n2 & n3 & !n4
# c3 & !n3 & !n4 & !reset
# c2 & n4;
_X002 = EXP( n0 & n1);
-- Node name is ':119' = 'c4'
-- Equation name is 'c4', location is LC117, type is buried.
c4 = DFFE( _EQ005 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = c3 & n0 & n1 & !n2 & n3 & !n4
# c4 & !n2 & !n4 & !reset & _X002
# c3 & n2 & n3 & !n4
# c4 & !n3 & !n4 & !reset
# c3 & n4;
_X002 = EXP( n0 & n1);
-- Node name is ':71' = 'flag'
-- Equation name is 'flag', location is LC123, type is buried.
flag = DFFE( _EQ006 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ006 = !flag & !n0 & !n2 & !n4 & t1
# !flag & !n1 & !n2 & !n4 & t1
# !flag & !n3 & !n4 & t1
# flag & !reset & t1;
-- Node name is ':118' = 'n0'
-- Equation name is 'n0', location is LC118, type is buried.
n0 = DFFE( _EQ007 $ !n4, GLOBAL( clk), VCC, VCC, VCC);
_EQ007 = n0 & n1 & !n2 & n3 & !n4
# !flag & !n0 & !n4 & t1
# n2 & n3 & !n4
# n0 & !n4 & _X003;
_X003 = EXP(!flag & t1);
-- Node name is ':117' = 'n1'
-- Equation name is 'n1', location is LC119, type is buried.
n1 = DFFE( _EQ008 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ008 = !flag & n1 & !n3 & !n4 & t1
# flag & n0 & !n1 & !n4 & _X004
# n0 & !n1 & !n4 & !t1 & _X004
# !n0 & n1 & !n4 & _X004;
_X004 = EXP( n2 & n3);
-- Node name is ':116' = 'n2'
-- Equation name is 'n2', location is LC120, type is buried.
n2 = DFFE( _EQ009 $ GND, GLOBAL( clk), VCC, VCC, VCC);
_EQ009 = flag & n0 & n1 & !n2 & !n3 & !n4
# n0 & n1 & !n2 & !n3 & !n4 & !t1
# !flag & n2 & !n3 & !n4 & t1
# !n1 & n2 & !n3 & !n4
# !n0 & n2 & !n3 & !n4;
-- Node name is ':115' = 'n3'
-- Equation name is 'n3', location is LC121, type is buried.
n3 = DFFE( _EQ010 $ _EQ011, GLOBAL( clk), VCC, VCC, VCC);
_EQ010 = n0 & n1 & n3 & !n4 & _X005
# flag & !_LC126 & !n4 & t1 & _X005
# !flag & n3 & !n4 & t1 & _X005
# n2 & n3 & !n4 & _X005;
_X005 = EXP(!_LC124 & !t1);
_EQ011 = !n4 & _X005;
_X005 = EXP(!_LC124 & !t1);
-- Node name is ':114' = 'n4'
-- Equation name is 'n4', location is LC122, type is buried.
n4 = TFFE(!_EQ012, GLOBAL( clk), VCC, VCC, VCC);
_EQ012 = n0 & n1 & n3 & !n4
# flag & !n4 & t1 & _X006
# !flag & !n3 & !n4 & t1
# n2 & n3 & !n4
# !n4 & !t1 & _X006;
_X006 = EXP( n0 & n1 & n2 & n3);
-- Node name is 'out' = ':157'
-- Equation name is 'out', type is output
out = DFFE( c4 $ GND, GLOBAL( clk), VCC, VCC, !_LC127);
-- Node name is '|lpm_add_sub:160|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC126', type is buried
_LC126 = LCELL( n3 $ _EQ013);
_EQ013 = n0 & n1 & n2;
-- Node name is '|lpm_add_sub:161|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC124', type is buried
_LC124 = LCELL( n3 $ _EQ014);
_EQ014 = n0 & n1 & n2;
-- Node name is '~128~1'
-- Equation name is '~128~1', location is LC116, type is buried.
-- synthesized logic cell
_LC116 = LCELL( _EQ015 $ GND);
_EQ015 = c1 & c4 & n2 & n3
# !c1 & !c4 & n2 & n3
# !c1 & !n3 & !n4 & !reset
# c1 & c4 & n4
# !c1 & !c4 & n4;
-- Node name is '~158~1'
-- Equation name is '~158~1', location is LC127, type is buried.
-- synthesized logic cell
_LC127 = LCELL( _EQ016 $ GND);
_EQ016 = !n1 & !n2 & !n4
# !n0 & !n2 & !n4
# !n3 & !n4;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information d:\so2006\cpld-pro\prog+max2\m15\chip1.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000E' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:00
Memory Allocated
-----------------
Peak memory allocated during compilation = 4,072K
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