chip1.v

扩频通信M序列,编码,通用VHDL语言

//////////2006.05.11 capture dsss 
module chip1(clk,out,reset,t1);//ok
input clk,reset,t1;
output out;
reg c1,c2,c3,c4,flag;
reg out;
reg[4:0]n;
reg red;
//reg[7:0]flag;
/*initial
  begin
    c1<=1;                                                                                                                                                                                                                                                                                                                    
    c2<=0;
    c3<=0;
    c4<=0;
    flag<=0;
   end
*/
always @(posedge clk)// up edg 
begin
    if(reset==1)//1+x+x^4//0xf590=1111 0101 1001 000B init 
       begin
          c1<=1;
          c2<=0;
          c3<=0;
          c4<=0;
         flag<=0;
     // light(red);

      end
  if(n>10)        //  move 1 bit  to left
      begin    
// for(n=2;n<=8;n=n+1);
          out<=c4;
          c4<=c3;
          c3<=c2;
          c2<=c1;
          c1<=c4^c1;     
         n<=0; 
       end 
   else            //n<10
       begin
          if(t1==1) // detect and change phase
             begin
               if(flag==0)   //first change phase
                  begin
                    n<=n+8;   //change phase to left 
                   // n<=0;     //delay  phase to right
                    flag<=1; //set flag, prevent repeat change phase 
                  end
               else
                  begin
                  n<=n+1;
                  end
              end  
           else 
             begin
               n<=n+1; 
             end 
      end
  if(t1==0)  //ti=0 flag=0,prevent repeat change phase 
     begin
      flag<=0;
     end
end
/*always @(posedge t1)// up edg 
   begin
   flag<=1;
     
   end
*/
/*task light(color);
 output color;
    begin
    color<=0;
     end
endtask
*/
endmodule

/*module chip2(t1,out);//ok
input t1;
output out;
//reg[7:0]n;
reg out;
always @(posedge t1)// up edg 
    begin
    //  defparam
   // n=n+1;
   out=~out;
     end
endmodule
*/

/*module chip1(clk, in, reset, out);
   input clk, in, reset;
   output out;

   reg out;
   reg state;

   parameter s0 = 0, s1 = 1;

   always @(state) 
   begin
	case (state)
		s0:
			out = 0;
		s1:
			out = 1;
		default:
			out = 0;
	endcase
   end
endmodule
*/