pci_bridge32.tlg

这是用pci-wishbone核和16450串口核在xilinx的fpga上实现的串口程序

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":112:42:112:47|Input port bit <3> of ta0_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":112:42:112:47|Input port bit <2> of ta0_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":112:42:112:47|Input port bit <1> of ta0_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":112:42:112:47|Input port bit <0> of ta0_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":114:42:114:47|Input port bit <19> of ta2_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":114:42:114:47|Input port bit <18> of ta2_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":114:42:114:47|Input port bit <17> of ta2_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":114:42:114:47|Input port bit <16> of ta2_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":114:42:114:47|Input port bit <15> of ta2_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":114:42:114:47|Input port bit <14> of ta2_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":114:42:114:47|Input port bit <13> of ta2_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":114:42:114:47|Input port bit <12> of ta2_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":114:42:114:47|Input port bit <11> of ta2_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":114:42:114:47|Input port bit <10> of ta2_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":114:42:114:47|Input port bit <9> of ta2_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":114:42:114:47|Input port bit <8> of ta2_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":114:42:114:47|Input port bit <7> of ta2_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":114:42:114:47|Input port bit <6> of ta2_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":114:42:114:47|Input port bit <5> of ta2_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":114:42:114:47|Input port bit <4> of ta2_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":114:42:114:47|Input port bit <3> of ta2_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":114:42:114:47|Input port bit <2> of ta2_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":114:42:114:47|Input port bit <1> of ta2_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":114:42:114:47|Input port bit <0> of ta2_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":115:42:115:47|Input port bit <19> of ta3_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":115:42:115:47|Input port bit <18> of ta3_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":115:42:115:47|Input port bit <17> of ta3_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":115:42:115:47|Input port bit <16> of ta3_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":115:42:115:47|Input port bit <15> of ta3_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":115:42:115:47|Input port bit <14> of ta3_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":115:42:115:47|Input port bit <13> of ta3_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":115:42:115:47|Input port bit <12> of ta3_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":115:42:115:47|Input port bit <11> of ta3_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":115:42:115:47|Input port bit <10> of ta3_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":115:42:115:47|Input port bit <9> of ta3_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":115:42:115:47|Input port bit <8> of ta3_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":115:42:115:47|Input port bit <7> of ta3_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":115:42:115:47|Input port bit <6> of ta3_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":115:42:115:47|Input port bit <5> of ta3_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":115:42:115:47|Input port bit <4> of ta3_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":115:42:115:47|Input port bit <3> of ta3_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":115:42:115:47|Input port bit <2> of ta3_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":115:42:115:47|Input port bit <1> of ta3_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":115:42:115:47|Input port bit <0> of ta3_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":116:42:116:47|Input port bit <19> of ta4_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":116:42:116:47|Input port bit <18> of ta4_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":116:42:116:47|Input port bit <17> of ta4_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":116:42:116:47|Input port bit <16> of ta4_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":116:42:116:47|Input port bit <15> of ta4_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":116:42:116:47|Input port bit <14> of ta4_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":116:42:116:47|Input port bit <13> of ta4_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":116:42:116:47|Input port bit <12> of ta4_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":116:42:116:47|Input port bit <11> of ta4_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":116:42:116:47|Input port bit <10> of ta4_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":116:42:116:47|Input port bit <9> of ta4_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":116:42:116:47|Input port bit <8> of ta4_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":116:42:116:47|Input port bit <7> of ta4_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":116:42:116:47|Input port bit <6> of ta4_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":116:42:116:47|Input port bit <5> of ta4_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":116:42:116:47|Input port bit <4> of ta4_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":116:42:116:47|Input port bit <3> of ta4_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":116:42:116:47|Input port bit <2> of ta4_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":116:42:116:47|Input port bit <1> of ta4_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":116:42:116:47|Input port bit <0> of ta4_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":117:42:117:47|Input port bit <19> of ta5_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":117:42:117:47|Input port bit <18> of ta5_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":117:42:117:47|Input port bit <17> of ta5_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":117:42:117:47|Input port bit <16> of ta5_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":117:42:117:47|Input port bit <15> of ta5_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":117:42:117:47|Input port bit <14> of ta5_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":117:42:117:47|Input port bit <13> of ta5_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":117:42:117:47|Input port bit <12> of ta5_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":117:42:117:47|Input port bit <11> of ta5_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":117:42:117:47|Input port bit <10> of ta5_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":117:42:117:47|Input port bit <9> of ta5_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":117:42:117:47|Input port bit <8> of ta5_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":117:42:117:47|Input port bit <7> of ta5_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":117:42:117:47|Input port bit <6> of ta5_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":117:42:117:47|Input port bit <5> of ta5_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":117:42:117:47|Input port bit <4> of ta5_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":117:42:117:47|Input port bit <3> of ta5_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":117:42:117:47|Input port bit <2> of ta5_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":117:42:117:47|Input port bit <1> of ta5_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":117:42:117:47|Input port bit <0> of ta5_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":118:13:118:20|Input port bit <5> of at_en_in[5:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":118:13:118:20|Input port bit <4> of at_en_in[5:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":118:13:118:20|Input port bit <3> of at_en_in[5:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":118:13:118:20|Input port bit <2> of at_en_in[5:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":118:13:118:20|Input port bit <0> of at_en_in[5:0] is unused

@W: CL159 :"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":100:42:100:48|Input bar0_in is unused
@W: CL159 :"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":102:42:102:48|Input bar2_in is unused
@W: CL159 :"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":103:42:103:48|Input bar3_in is unused
@W: CL159 :"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":104:42:104:48|Input bar4_in is unused
@W: CL159 :"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":105:42:105:48|Input bar5_in is unused
@W: CL159 :"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":106:42:106:47|Input am0_in is unused
@W: CL159 :"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":108:42:108:47|Input am2_in is unused
@W: CL159 :"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":109:42:109:47|Input am3_in is unused
@W: CL159 :"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":110:42:110:47|Input am4_in is unused
@W: CL159 :"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":111:42:111:47|In