pci_bridge32.tlg

这是用pci-wishbone核和16450串口核在xilinx的fpga上实现的串口程序

@W:"D:\Program Files\Synplicity\Synplify_76\bin\..\lib\xilinx\unisim.v":6301:17:6301:19|Input port bit <12> of DIA[15:0] is unused

@W:"D:\Program Files\Synplicity\Synplify_76\bin\..\lib\xilinx\unisim.v":6301:17:6301:19|Input port bit <11> of DIA[15:0] is unused

@W:"D:\Program Files\Synplicity\Synplify_76\bin\..\lib\xilinx\unisim.v":6301:17:6301:19|Input port bit <10> of DIA[15:0] is unused

@W:"D:\Program Files\Synplicity\Synplify_76\bin\..\lib\xilinx\unisim.v":6301:17:6301:19|Input port bit <9> of DIA[15:0] is unused

@W:"D:\Program Files\Synplicity\Synplify_76\bin\..\lib\xilinx\unisim.v":6301:17:6301:19|Input port bit <8> of DIA[15:0] is unused

@W:"D:\Program Files\Synplicity\Synplify_76\bin\..\lib\xilinx\unisim.v":6301:17:6301:19|Input port bit <7> of DIA[15:0] is unused

@W:"D:\Program Files\Synplicity\Synplify_76\bin\..\lib\xilinx\unisim.v":6301:17:6301:19|Input port bit <6> of DIA[15:0] is unused

@W:"D:\Program Files\Synplicity\Synplify_76\bin\..\lib\xilinx\unisim.v":6301:17:6301:19|Input port bit <5> of DIA[15:0] is unused

@W:"D:\Program Files\Synplicity\Synplify_76\bin\..\lib\xilinx\unisim.v":6301:17:6301:19|Input port bit <4> of DIA[15:0] is unused

@W:"D:\Program Files\Synplicity\Synplify_76\bin\..\lib\xilinx\unisim.v":6301:17:6301:19|Input port bit <3> of DIA[15:0] is unused

@W:"D:\Program Files\Synplicity\Synplify_76\bin\..\lib\xilinx\unisim.v":6301:17:6301:19|Input port bit <2> of DIA[15:0] is unused

@W:"D:\Program Files\Synplicity\Synplify_76\bin\..\lib\xilinx\unisim.v":6301:17:6301:19|Input port bit <1> of DIA[15:0] is unused

@W:"D:\Program Files\Synplicity\Synplify_76\bin\..\lib\xilinx\unisim.v":6301:17:6301:19|Input port bit <0> of DIA[15:0] is unused

@W:"D:\Program Files\Synplicity\Synplify_76\bin\..\lib\xilinx\unisim.v":6304:16:6304:20|Input port bit <7> of ADDRB[7:0] is unused

@W:"D:\Program Files\Synplicity\Synplify_76\bin\..\lib\xilinx\unisim.v":6304:16:6304:20|Input port bit <6> of ADDRB[7:0] is unused

@W:"D:\Program Files\Synplicity\Synplify_76\bin\..\lib\xilinx\unisim.v":6304:16:6304:20|Input port bit <5> of ADDRB[7:0] is unused

@W:"D:\Program Files\Synplicity\Synplify_76\bin\..\lib\xilinx\unisim.v":6304:16:6304:20|Input port bit <4> of ADDRB[7:0] is unused

@W:"D:\Program Files\Synplicity\Synplify_76\bin\..\lib\xilinx\unisim.v":6304:16:6304:20|Input port bit <3> of ADDRB[7:0] is unused

@W:"D:\Program Files\Synplicity\Synplify_76\bin\..\lib\xilinx\unisim.v":6304:16:6304:20|Input port bit <2> of ADDRB[7:0] is unused

@W:"D:\Program Files\Synplicity\Synplify_76\bin\..\lib\xilinx\unisim.v":6304:16:6304:20|Input port bit <1> of ADDRB[7:0] is unused

@W:"D:\Program Files\Synplicity\Synplify_76\bin\..\lib\xilinx\unisim.v":6304:16:6304:20|Input port bit <0> of ADDRB[7:0] is unused

@W:"D:\Program Files\Synplicity\Synplify_76\bin\..\lib\xilinx\unisim.v":6305:17:6305:19|Input port bit <15> of DIB[15:0] is unused

@W:"D:\Program Files\Synplicity\Synplify_76\bin\..\lib\xilinx\unisim.v":6305:17:6305:19|Input port bit <14> of DIB[15:0] is unused

@W:"D:\Program Files\Synplicity\Synplify_76\bin\..\lib\xilinx\unisim.v":6305:17:6305:19|Input port bit <13> of DIB[15:0] is unused

@W:"D:\Program Files\Synplicity\Synplify_76\bin\..\lib\xilinx\unisim.v":6305:17:6305:19|Input port bit <12> of DIB[15:0] is unused

@W:"D:\Program Files\Synplicity\Synplify_76\bin\..\lib\xilinx\unisim.v":6305:17:6305:19|Input port bit <11> of DIB[15:0] is unused

@W:"D:\Program Files\Synplicity\Synplify_76\bin\..\lib\xilinx\unisim.v":6305:17:6305:19|Input port bit <10> of DIB[15:0] is unused

@W:"D:\Program Files\Synplicity\Synplify_76\bin\..\lib\xilinx\unisim.v":6305:17:6305:19|Input port bit <9> of DIB[15:0] is unused

@W:"D:\Program Files\Synplicity\Synplify_76\bin\..\lib\xilinx\unisim.v":6305:17:6305:19|Input port bit <8> of DIB[15:0] is unused

@W:"D:\Program Files\Synplicity\Synplify_76\bin\..\lib\xilinx\unisim.v":6305:17:6305:19|Input port bit <7> of DIB[15:0] is unused

@W:"D:\Program Files\Synplicity\Synplify_76\bin\..\lib\xilinx\unisim.v":6305:17:6305:19|Input port bit <6> of DIB[15:0] is unused

@W:"D:\Program Files\Synplicity\Synplify_76\bin\..\lib\xilinx\unisim.v":6305:17:6305:19|Input port bit <5> of DIB[15:0] is unused

@W:"D:\Program Files\Synplicity\Synplify_76\bin\..\lib\xilinx\unisim.v":6305:17:6305:19|Input port bit <4> of DIB[15:0] is unused

@W:"D:\Program Files\Synplicity\Synplify_76\bin\..\lib\xilinx\unisim.v":6305:17:6305:19|Input port bit <3> of DIB[15:0] is unused

@W:"D:\Program Files\Synplicity\Synplify_76\bin\..\lib\xilinx\unisim.v":6305:17:6305:19|Input port bit <2> of DIB[15:0] is unused

@W:"D:\Program Files\Synplicity\Synplify_76\bin\..\lib\xilinx\unisim.v":6305:17:6305:19|Input port bit <1> of DIB[15:0] is unused

@W:"D:\Program Files\Synplicity\Synplify_76\bin\..\lib\xilinx\unisim.v":6305:17:6305:19|Input port bit <0> of DIB[15:0] is unused

Synthesizing module pci_wb_tpram
	aw=32'b00000000000000000000000000001000
	dw=32'b00000000000000000000000000101000
   Generated name = pci_wb_tpram_8_40
@W: CL159 :"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_tpram.v":143:8:143:11|Input oe_a is unused
@W: CL159 :"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_tpram.v":151:8:151:11|Input oe_b is unused
Synthesizing module pci_synchronizer_flop
	width=32'b00000000000000000000000000000111
	reset_val=32'b00000000000000000000000000000000
   Generated name = pci_synchronizer_flop_7_0
Synthesizing module pci_synchronizer_flop
	width=32'b00000000000000000000000000000111
	reset_val=32'b00000000000000000000000000000011
   Generated name = pci_synchronizer_flop_7_3
Synthesizing module pci_wbw_fifo_control
	ADDR_LENGTH=32'b00000000000000000000000000000111
   Generated name = pci_wbw_fifo_control_7
Synthesizing module pci_wbr_fifo_control
	ADDR_LENGTH=32'b00000000000000000000000000000111
   Generated name = pci_wbr_fifo_control_7
Synthesizing module pci_synchronizer_flop
	width=32'b00000000000000000000000000000110
	reset_val=32'b00000000000000000000000000000000
   Generated name = pci_synchronizer_flop_6_0
Synthesizing module pci_wbw_wbr_fifos
Synthesizing module pci_wb_decoder
	decode_len=32'b00000000000000000000000000010100
   Generated name = pci_wb_decoder_20
@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_decoder.v":96:27:96:35|Input port bit <31> of tran_addr[31:12] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_decoder.v":96:27:96:35|Input port bit <30> of tran_addr[31:12] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_decoder.v":96:27:96:35|Input port bit <29> of tran_addr[31:12] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_decoder.v":96:27:96:35|Input port bit <28> of tran_addr[31:12] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_decoder.v":96:27:96:35|Input port bit <27> of tran_addr[31:12] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_decoder.v":96:27:96:35|Input port bit <26> of tran_addr[31:12] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_decoder.v":96:27:96:35|Input port bit <25> of tran_addr[31:12] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_decoder.v":96:27:96:35|Input port bit <24> of tran_addr[31:12] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_decoder.v":96:27:96:35|Input port bit <23> of tran_addr[31:12] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_decoder.v":96:27:96:35|Input port bit <22> of tran_addr[31:12] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_decoder.v":96:27:96:35|Input port bit <21> of tran_addr[31:12] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_decoder.v":96:27:96:35|Input port bit <20> of tran_addr[31:12] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_decoder.v":96:27:96:35|Input port bit <19> of tran_addr[31:12] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_decoder.v":96:27:96:35|Input port bit <18> of tran_addr[31:12] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_decoder.v":96:27:96:35|Input port bit <17> of tran_addr[31:12] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_decoder.v":96:27:96:35|Input port bit <16> of tran_addr[31:12] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_decoder.v":96:27:96:35|Input port bit <15> of tran_addr[31:12] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_decoder.v":96:27:96:35|Input port bit <14> of tran_addr[31:12] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_decoder.v":96:27:96:35|Input port bit <13> of tran_addr[31:12] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_decoder.v":96:27:96:35|Input port bit <12> of tran_addr[31:12] is unused

@W: CL159 :"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_decoder.v":96:27:96:35|Input tran_addr is unused
@W: CL159 :"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_decoder.v":99:6:99:10|Input at_en is unused
Synthesizing module pci_wb_addr_mux
@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":100:42:100:48|Input port bit <19> of bar0_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":100:42:100:48|Input port bit <18> of bar0_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":100:42:100:48|Input port bit <17> of bar0_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":100:42:100:48|Input port bit <16> of bar0_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":100:42:100:48|Input port bit <15> of bar0_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":100:42:100:48|Input port bit <14> of bar0_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":100:42:100:48|Input port bit <13> of bar0_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":100:42:100:48|Input port bit <12> of bar0_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":100:42:100:48|Input port bit <11> of bar0_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":100:42:100:48|Input port bit <10> of bar0_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":100:42:100:48|Input port bit <9> of bar0_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":100:42:100:48|Input port bit <8> of bar0_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":100:42:100:48|Input port bit <7> of bar0_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":100:42:100:48|Input port bit <6> of bar0_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":100:42:100:48|Input port bit <5> of bar0_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":100:42:100:48|Input port bit <4> of bar0_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":100:42:100:48|Input port bit <3> of bar0_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":100:42:100:48|Input port bit <2> of bar0_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":100:42:100:48|Input port bit <1> of bar0_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":100:42:100:48|Input port bit <0> of bar0_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":102:42:102:48|Input port bit <19> of bar2_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":102:42:102:48|Input port bit <18> of bar2_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":102:42:102:48|Input port bit <17> of bar2_in[19:0] is unused

@W:"F:\lizheng\FiberOptical\FPGA\PCI_Bridge_Guest_UART\pci_wb_addr_mux.v":102:42:102:48|Input port bit <16> of bar2_in[19:0] is unused