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MVBC VHDL代码．．实现多功能车辆总线的通信

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Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "mvbif.v"
Module <mvbif> compiled
No errors in compilation
Analysis of file <mvbif.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <mvbif>.
Module <mvbif> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <mvbif>.
    Related source file is mvbif.v.
    Found 24-bit register for signal <addr_mvbc>.
    Found 1-bit register for signal <wr_mvbc_n>.
    Found 1-bit register for signal <rdy2cpu_n>.
    Found 1-bit register for signal <rd_mvbc_n>.
    Found 1-bit register for signal <cs_mvbc_n>.
    Found 3-bit up counter for signal <counter>.
    Found 1-bit register for signal <Delay>.
    Summary:
	inferred   1 Counter(s).
	inferred  29 D-type flip-flop(s).
Unit <mvbif> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 6
  1-bit register                   : 5
  24-bit register                  : 1
# Counters                         : 1
  3-bit up counter                 : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================


=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <mvbif> ...
Loading device for application Xst from file '2s300e.nph' in environment C:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block mvbif, actual ratio is 0.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s300epq208-6 

 Number of Slices:                      19  out of   3072     0%  
 Number of Slice Flip Flops:            32  out of   6144     0%  
 Number of 4 input LUTs:                 9  out of   6144     0%  
 Number of bonded IOBs:                 71  out of    146    48%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 32    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 4.337ns (Maximum Frequency: 230.574MHz)
   Minimum input arrival time before clock: 4.082ns
   Maximum output required time after clock: 6.514ns
   Maximum combinational path delay: 9.325ns

=========================================================================
Completed process "Synthesize".



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Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd d:\2006\fpga_design\mvbc3\mvbc3/_ngo -i
-p xc2s300e-pq208-6 mvbif.ngc mvbif.ngd 

Reading NGO file "d:/2006/fpga_design/mvbc3/mvbc3/mvbif.ngc" ...
Reading component libraries for design expansion...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Total memory usage is 38668 kilobytes

Writing NGD file "mvbif.ngd" ...

Writing NGDBUILD log file "mvbif.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "2s300epq208-6".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:         4 out of  6,144    1%
  Number of 4 input LUTs:             7 out of  6,144    1%
Logic Distribution:
    Number of occupied Slices:                           5 out of  3,072    1%
    Number of Slices containing only related logic:      5 out of      5  100%
    Number of Slices containing unrelated logic:         0 out of      5    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number of 4 input LUTs:         7 out of  6,144    1%
   Number of bonded IOBs:            71 out of    142   50%
      IOB Flip Flops:                              28
   Number of GCLKs:                   1 out of      4   25%
   Number of GCLKIOBs:                1 out of      4   25%

Total equivalent gate count for design:  298
Additional JTAG gate count for IOBs:  3,456
Peak Memory Usage:  67 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "mvbif_map.mrp" for details.
Completed process "Map".

Mapping Module mvbif . . .
MAP command line:
map -intstyle ise -p xc2s300e-pq208-6 -cm area -pr b -k 4 -c 100 -tx off -o mvbif_map.ncd mvbif.ngd mvbif.pcf
Mapping Module mvbif: DONE



Started process "Place & Route".





Constraints file: mvbif.pcf

Loading device database for application Par from file "mvbif_map.ncd".
   "mvbif" is an NCD, version 2.38, device xc2s300e, package pq208, speed -6
Loading device for application Par from file '2s300e.nph' in environment
C:/Xilinx.
Device speed data version:  PRODUCTION 1.17 2003-06-19.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs            71 out of 142    50%
      Number of LOCed External IOBs    0 out of 71      0%

   Number of SLICEs                    5 out of 3072    1%

   Number of GCLKs                     1 out of 4      25%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:9897b7) REAL time: 0 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8
.
Phase 5.8 (Checksum:9aa1bd) REAL time: 0 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 0 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs 

Writing design to file mvbif.ncd.

Total REAL time to Placer completion: 0 secs 
Total CPU time to Placer completion: 1 secs 


Phase 1: 89 unrouted;       REAL time: 2 secs 

Phase 2: 58 unrouted;       REAL time: 2 secs 

Phase 3: 6 unrouted;       REAL time: 2 secs 

Phase 4: 0 unrouted;       REAL time: 2 secs 

Total REAL time to Router completion: 2 secs 
Total CPU time to Router completion: 1 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|         clk_BUFGP          |  Global  |   31   |  0.211     |  0.657      |
+----------------------------+----------+--------+------------+-------------+

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 2 secs 
Total CPU time to PAR completion: 2 secs 

Peak Memory Usage:  57 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file mvbif.ncd.


PAR done.
Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".


Analysis completed Tue Jan 09 19:37:38 2007
--------------------------------------------------------------------------------

Generating Report ...

Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module mvbif . . .
PAR command line: par -w -intstyle ise -ol std -t 1 mvbif_map.ncd mvbif.ncd mvbif.pcf
PAR completed successfully



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Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling source file "mvbif.v"
Module <mvbif> compiled
No errors in compilation
Analysis of file <mvbif.prj> succeeded.
 

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <mvbif>.
Module <mvbif> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <mvbif>.
    Related source file is mvbif.v.
    Found 24-bit register for signal <addr_mvbc>.
    Found 1-bit register for signal <wr_mvbc_n>.
    Found 1-bit register for signal <rdy2cpu_n>.
    Found 1-bit register for signal <rd_mvbc_n>.
    Found 1-bit register for signal <cs_mvbc_n>.
    Found 3-bit up counter for signal <counter>.
    Found 1-bit register for signal <Delay>.
    Summary:
	inferred   1 Counter(s).
	inferred  29 D-type flip-flop(s).
Unit <mvbif> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 6
  1-bit register                   : 5
  24-bit register                  : 1
# Counters                         : 1
  3-bit up counter                 : 1

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================


=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <mvbif> ...
Loading device for application Xst from file '2s300e.nph' in environment C:/Xilinx.

Mapping all equations...