__projnav.log

来自「MVBC VHDL代码．．实现多功能车辆总线的通信」· LOG 代码 · 共 2,079 行 · 第 1/5 页

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=========================================================================*                          HDL Compilation                              *=========================================================================Compiling source file "mvbif.v"Module <mvbif> compiledNo errors in compilationAnalysis of file <mvbif.prj> succeeded. =========================================================================*                            HDL Analysis                               *=========================================================================Analyzing top module <mvbif>.Module <mvbif> is correct for synthesis. =========================================================================*                           HDL Synthesis                               *=========================================================================Synthesizing Unit <mvbif>.    Related source file is mvbif.v.WARNING:Xst:647 - Input <rdy2mvbc_n> is never used.    Found 24-bit register for signal <addr_mvbc>.    Found 1-bit register for signal <wr_mvbc_n>.    Found 1-bit register for signal <rdy2cpu_n>.    Found 1-bit register for signal <rd_mvbc_n>.    Found 1-bit register for signal <cs_mvbc_n>.    Found 3-bit up counter for signal <counter>.    Found 1-bit register for signal <overflow>.    Summary:	inferred   1 Counter(s).	inferred  29 D-type flip-flop(s).Unit <mvbif> synthesized.=========================================================================HDL Synthesis ReportMacro Statistics# Registers                        : 6  1-bit register                   : 5  24-bit register                  : 1# Counters                         : 1  3-bit up counter                 : 1==================================================================================================================================================*                       Advanced HDL Synthesis                          *==================================================================================================================================================*                         Low Level Synthesis                           *=========================================================================Optimizing unit <mvbif> ...Loading device for application Xst from file '2s300e.nph' in environment C:/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block mvbif, actual ratio is 0.=========================================================================*                            Final Report                               *=========================================================================Device utilization summary:---------------------------Selected Device : 2s300epq208-6  Number of Slices:                      19  out of   3072     0%   Number of Slice Flip Flops:            32  out of   6144     0%   Number of 4 input LUTs:                 7  out of   6144     0%   Number of bonded IOBs:                 70  out of    146    47%   Number of GCLKs:                        1  out of      4    25%  =========================================================================TIMING REPORTClock Information:-----------------------------------------------------+------------------------+-------+Clock Signal                       | Clock buffer(FF name)  | Load  |-----------------------------------+------------------------+-------+clk                                | BUFGP                  | 32    |-----------------------------------+------------------------+-------+Timing Summary:---------------Speed Grade: -6   Minimum period: 3.877ns (Maximum Frequency: 257.931MHz)   Minimum input arrival time before clock: 4.612ns   Maximum output required time after clock: 6.514ns   Maximum combinational path delay: 10.025ns=========================================================================Completed process "Synthesize".

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Started process "Synthesize".=========================================================================*                          HDL Compilation                              *=========================================================================Compiling source file "mvbif.v"Module <mvbif> compiledNo errors in compilationAnalysis of file <mvbif.prj> succeeded. =========================================================================*                            HDL Analysis                               *=========================================================================Analyzing top module <mvbif>.Module <mvbif> is correct for synthesis. =========================================================================*                           HDL Synthesis                               *=========================================================================Synthesizing Unit <mvbif>.    Related source file is mvbif.v.WARNING:Xst:647 - Input <rdy2mvbc_n> is never used.    Found 24-bit register for signal <addr_mvbc>.    Found 1-bit register for signal <wr_mvbc_n>.    Found 1-bit register for signal <rdy2cpu_n>.    Found 1-bit register for signal <rd_mvbc_n>.    Found 1-bit register for signal <cs_mvbc_n>.    Found 3-bit up counter for signal <counter>.    Found 1-bit register for signal <overflow>.    Summary:	inferred   1 Counter(s).	inferred  29 D-type flip-flop(s).Unit <mvbif> synthesized.=========================================================================HDL Synthesis ReportMacro Statistics# Registers                        : 6  1-bit register                   : 5  24-bit register                  : 1# Counters                         : 1  3-bit up counter                 : 1==================================================================================================================================================*                       Advanced HDL Synthesis                          *==================================================================================================================================================*                         Low Level Synthesis                           *=========================================================================Optimizing unit <mvbif> ...Loading device for application Xst from file '2s300e.nph' in environment C:/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block mvbif, actual ratio is 0.=========================================================================*                            Final Report                               *=========================================================================Device utilization summary:---------------------------Selected Device : 2s300epq208-6  Number of Slices:                      19  out of   3072     0%   Number of Slice Flip Flops:            32  out of   6144     0%   Number of 4 input LUTs:                 7  out of   6144     0%   Number of bonded IOBs:                 70  out of    146    47%   Number of GCLKs:                        1  out of      4    25%  =========================================================================TIMING REPORTClock Information:-----------------------------------------------------+------------------------+-------+Clock Signal                       | Clock buffer(FF name)  | Load  |-----------------------------------+------------------------+-------+clk                                | BUFGP                  | 32    |-----------------------------------+------------------------+-------+Timing Summary:---------------Speed Grade: -6   Minimum period: 3.877ns (Maximum Frequency: 257.931MHz)   Minimum input arrival time before clock: 4.612ns   Maximum output required time after clock: 6.514ns   Maximum combinational path delay: 10.025ns=========================================================================Completed process "Synthesize".

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Started process "Synthesize".=========================================================================*                          HDL Compilation                              *=========================================================================Compiling source file "mvbif.v"Module <mvbif> compiledNo errors in compilationAnalysis of file <mvbif.prj> succeeded. =========================================================================*                            HDL Analysis                               *=========================================================================Analyzing top module <mvbif>.Module <mvbif> is correct for synthesis. =========================================================================*                           HDL Synthesis                               *=========================================================================Synthesizing Unit <mvbif>.    Related source file is mvbif.v.WARNING:Xst:647 - Input <rdy2mvbc_n> is never used.    Found 24-bit register for signal <addr_mvbc>.    Found 1-bit register for signal <wr_mvbc_n>.    Found 1-bit register for signal <rdy2cpu_n>.    Found 1-bit register for signal <rd_mvbc_n>.    Found 1-bit register for signal <cs_mvbc_n>.    Found 3-bit up counter for signal <counter>.    Found 1-bit register for signal <overflow>.    Summary:	inferred   1 Counter(s).	inferred  29 D-type flip-flop(s).Unit <mvbif> synthesized.=========================================================================HDL Synthesis ReportMacro Statistics# Registers                        : 6  1-bit register                   : 5  24-bit register                  : 1# Counters                         : 1  3-bit up counter                 : 1==================================================================================================================================================*                       Advanced HDL Synthesis                          *==================================================================================================================================================*                         Low Level Synthesis                           *=========================================================================Optimizing unit <mvbif> ...Loading device for application Xst from file '2s300e.nph' in environment C:/Xilinx.Mapping all equations...Building and optimizing final netlist ...Found area constraint ratio of 100 (+ 5) on block mvbif, actual ratio is 0.=========================================================================*                            Final Report                               *=========================================================================Device utilization summary:---------------------------Selected Device : 2s300epq208-6  Number of Slices:                      19  out of   3072     0%   Number of Slice Flip Flops:            32  out of   6144     0%   Number of 4 input LUTs:                 7  out of   6144     0%   Number of bonded IOBs:                 70  out of    146    47%   Number of GCLKs:                        1  out of      4    25%  =========================================================================TIMING REPORTClock Information:-----------------------------------------------------+------------------------+-------+Clock Signal                       | Clock buffer(FF name)  | Load  |-----------------------------------+------------------------+-------+clk                                | BUFGP                  | 32    |-----------------------------------+------------------------+-------+Timing Summary:---------------Speed Grade: -6   Minimum period: 3.877ns (Maximum Frequency: 257.931MHz)   Minimum input arrival time before clock: 4.612ns   Maximum output required time after clock: 6.514ns   Maximum combinational path delay: 10.025ns=========================================================================Completed process "Synthesize".

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Started process "Synthesize".=========================================================================*                          HDL Compilation                              *=========================================================================Compiling source file "mvbif.v"Module <mvbif> compiledNo errors in compilationAnalysis of file <mvbif.prj> succeeded. =========================================================================*                            HDL Analysis                               *=========================================================================Analyzing top module <mvbif>.Module <mvbif> is correct for synthesis. =========================================================================*                           HDL Synthesis                               *=========================================================================Synthesizing Unit <mvbif>.    Related source file is mvbif.v.WARNING:Xst:647 - Input <rdy2mvbc_n> is never used.    Found 24-bit register for signal <addr_mvbc>.    Found 1-bit register for signal <wr_mvbc_n>.    Found 1-bit register for signal <rdy2cpu_n>.    Found 1-bit register for signal <rd_mvbc_n>.    Found 1-bit register for signal <cs_mvbc_n>.    Found 3-bit up counter for signal <counter>.    Found 1-bit register for signal <Delay>.    Found 1-bit register for signal <overflow>.    Summary:	inferred   1 Counter(s).	inferred  30 D-type flip-flop(s).Unit <mvbif> synthesized.=========================================================================HDL Synthes
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