anc_edh_processor.vhd

XAPP299 version 1.0 reference design files

        ld_dc:          in    std_ulogic;       -- load DC register
        ld_udw:         in    std_ulogic;       -- loads the UDW RAM
        udw_wr_adr:     in    udwadr_type;      -- UDW RAM write address
        in_trs:         in    std_ulogic;       -- asserted during TRS symbols in video stream
        in_f:           in    std_ulogic;       -- field indicator
        in_v:           in    std_ulogic;       -- vertical blanking indicator
        in_h:           in    std_ulogic;       -- horizontal blanking indicator
        in_hcnt:        in    hpos_type;        -- horizontal position
        in_vcnt:        in    vpos_type;        -- vertical position
        in_sync_switch: in    std_ulogic;       -- synchronous switching line indicator
        in_eav_next:    in    std_ulogic;       -- indicates that next word is first word of an EAV
        in_sav_next:    in    std_ulogic;       -- indicates that next word is first word of an SAV
        in_xyz_word:    in    std_ulogic;       -- indicates that current word is XYZ word of a TRS
        in_anc_next:    in    std_ulogic;       -- indicates that next word is first word of ANC packet
        in_edh_next:    in    std_ulogic;       -- indicates that next word is first word of EDH packet
        in_edh_loc:     in    std_ulogic;       -- asserted when next word is beginning of EDH packet location
        vid_out:        out   video_type;       -- output video data
        pkt_in_empty:   out   std_ulogic;       -- module is ready for input packet to be loaded
        out_trs:        out   std_ulogic;       -- "delayed" in_trs signal
        out_f:          out   std_ulogic;       -- "delayed" in_f signal
        out_v:          out   std_ulogic;       -- "delayed" in_v signal
        out_h:          out   std_ulogic;       -- "delayed" in_h signal
        out_hcnt:       out   hpos_type;        -- "delayed" in_hcnt signal
        out_vcnt:       out   vpos_type;        -- "delayed" in_vcnt signal
        out_sync_switch:out   std_ulogic;       -- "delayed" in_sync_switch signal
        out_eav_next:   out   std_ulogic;       -- "delayed" in_eav_next signal
        out_sav_next:   out   std_ulogic;       -- "delayed" in_sav_next signal
        out_xyz_word:   out   std_ulogic;       -- "delayed" in_xyz_word signal
        out_anc_next:   out   std_ulogic;       -- "delayed" in_anc_next signal
        out_edh_next:   out   std_ulogic;       -- "delayed" in_edh_next signal
        out_edh_loc:    out   std_ulogic);      -- "delayed" in_edh_loc signal
end component;

component edh_gen
    port (
        clk:            in  std_ulogic;         -- clock input
        ce:             in  std_ulogic;         -- clock enable
        rst:            in  std_ulogic;         -- async reset input
        vid_in:         in  video_type;         -- input video port 
        std:            in  vidstd_type;        -- video standard
        locked:         in  std_ulogic;         -- flywheel is locked
        flag_bus:       in  edh_flgset_type;    -- input flag bus from edh_flags
        edh_missing:    in  std_ulogic;         -- indicates no EDH packet was found in input video
        in_trs:         in  std_ulogic;         -- asserted during TRS symbol
        in_f:           in  std_ulogic;         -- field bit
        in_v:           in  std_ulogic;         -- vertical blanking bit
        in_h:           in  std_ulogic;         -- horizontal blanking bit
        in_hcnt:        in  hpos_type;          -- current horizontal position
        in_vcnt:        in  vpos_type;          -- current vertical position
        in_sync_switch: in  std_ulogic;         -- sync switching interval indicator
        in_eav_next:    in  std_ulogic;         -- asserted when next word is 1st word of EAV
        in_sav_next:    in  std_ulogic;         -- asserted when next word is 1st word of SAV
        in_xyz_word:    in  std_ulogic;         -- asserted during XYZ word of TRS
        in_anc_next:    in  std_ulogic;         -- asserted when next word is 1st word of ANC packet
        in_edh_next:    in  std_ulogic;         -- asserted when next word is 1st word of EDH packet
        in_edh_loc:     in  std_ulogic;         -- next word is 1st word of an EDH packet location
        vid_out:        out video_type;         -- output video data
        ap_flag_word:   out std_ulogic;         -- selects the active-picture error flag set for flag_bus
        ff_flag_word:   out std_ulogic;         -- selects the full-field error flag set for flag_bus
        anc_flag_word:  out std_ulogic;         -- selects the anc error flag set for the flag_bus
        edh_packet:     out std_ulogic;         -- asserted during all words of a generated EDH packet
        out_trs:        out std_ulogic;         -- asserted during TRS symbols
        out_f:          out std_ulogic;         -- field indicator
        out_v:          out std_ulogic;         -- vertical blanking indicator
        out_h:          out std_ulogic;         -- horizontal blanking indicator
        out_hcnt:       out hpos_type;          -- horizontal position
        out_vcnt:       out vpos_type;          -- vertical position        
        out_sync_switch:out std_ulogic;         -- synchronous swithcing interval indicator     
        out_eav_next:   out std_ulogic;         -- asserted when next word is first word of an EAV      
        out_sav_next:   out std_ulogic;         -- asserted when next word is first word of an SAV      
        out_xyz_word:   out std_ulogic;         -- asserted during the XYZ word of a TRS symbol
        out_anc_next:   out std_ulogic;         -- asserted when next word is first word of an ANC packet       
        out_edh_next:   out std_ulogic);        -- asserted when next word is first word of an EDH packet
end component;

begin
	
	VCC <= '1';

    --
    -- video_decoder module
    --
    -- This module is from the XAPP625 refernce design. The module determines 
    -- the video standard of the input video stream and decodes the video timing
    -- information.
    --

    DEC : video_decode
        port map (
            clk                 => clk,
            ce                  => ce,
            rst                 => rst,
            vid_in              => vid_in,
            reacquire           => reacquire,
            en_sync_switch      => en_sync_switch,
            en_trs_blank        => en_trs_blank,
            std                 => dec_std,
            std_locked          => dec_std_locked,
            trs                 => dec_trs,
            vid_out             => dec_vid,
            field               => dec_f,
            v_blank             => dec_v,
            h_blank             => dec_h,
            horz_count          => dec_hcnt,
            vert_count          => dec_vcnt,
            sync_switch         => dec_sync_switch,
            locked              => dec_locked,
            eav_next            => dec_eav_next,
            sav_next            => dec_sav_next,
            xyz_word            => dec_xyz_word,
            anc_next            => dec_anc_next,
            edh_next            => dec_edh_next);

    --
    -- edh_crc module
    --
    -- This module computes the CRC values for the incoming video stream, vid_in.
    -- Also, the module generates valid signals for both CRC values based on the
    -- locked signal. If locked rises during a field, the CRC is considered to 
    -- be invalid.

    CRC : edh_crc
        port map (
            clk                 => clk,
            ce                  => ce,
            rst                 => rst,
            f                   => dec_f,
            h                   => dec_h,
            eav_next            => dec_eav_next,
            xyz_word            => dec_xyz_word,
            vid_in              => dec_vid,
            vcnt                => dec_vcnt,
            std                 => dec_std,
            locked              => dec_locked,
            ap_crc              => ap_crc,
            ap_crc_valid        => ap_crc_valid,
            ff_crc              => ff_crc,
            ff_crc_valid        => ff_crc_valid);

    --
    -- edh_rx module
    --
    -- This module processes EDH packets found in the incoming video stream. The
    -- CRC words and valid flags are captured from the packet. Various error 
    -- flags related to errors found in the packet are generated.
    --
    EDHRX : edh_rx
        port map (
            clk                 => clk,
            ce                  => ce,
            rst                 => rst,
            rx_edh_next         => dec_edh_next,
            vid_in              => dec_vid,
            edh_next            => tx_edh_next,
            reg_flags           => VCC,
            ap_crc_valid        => rx_ap_crc_valid,
            ap_crc              => rx_ap_crc,
            ff_crc_valid        => rx_ff_crc_valid,
            ff_crc              => rx_ff_crc,
            edh_missing         => edh_missing,
            edh_parity_err      => edh_parity_err,
            edh_chksum_err      => edh_chksum_err,
            edh_format_err      => edh_format_err,
            in_ap_flags         => in_ap_flags,
            in_ff_flags         => in_ff_flags,
            in_anc_flags        => in_anc_flags,
            rx_ap_flags         => rx_ap_flags,
            rx_ff_flags         => rx_ff_flags,
            rx_anc_flags        => rx_anc_flags);

    --
    -- edh_loc module
    --
    -- This module locates the beginning of an EDH packet in the incoming video
    -- stream. It asserts the tx_edh_next siganl the sample before the EDH 
    -- packet begins on vid_in.
    --
    LOC : edh_loc
        port map (
            clk                 => clk,
            ce                  => ce,
            rst                 => rst,
            f                   => dec_f,
            vcnt                => dec_vcnt,
            hcnt                => dec_hcnt,
            std                 => dec_std,
            edh_next            => tx_edh_next);

    --
    -- anc_rx
    --
    -- This module calculates a checksum value for each ANC packet in the video
    -- stream and compares this checksum with the CS word in the ANC packet. If
    -- a difference is found, the anc_edh_local signal is asserted and stays
    -- asserted until the edh_packet signal indicates that the next EDH packet 
    -- has been sent.
    --
    ANCRX : anc_rx
        port map (
            clk                 => clk,
            ce                  => ce,
            rst                 => rst,
            locked              => dec_locked,
            rx_anc_next         => dec_anc_next,
            rx_edh_next         => dec_edh_next,
            edh_packet          => tx_edh_packet,
            vid_in              => dec_vid,
            anc_edh_local       => anc_edh_local);


    --
    -- edh_flags module
    --
    -- This module creates the error flags that are included in the new
    -- EDH packet created by the GEN module. It also captures those flags until 
    -- the next EDH packet and provides them as outputs.
    --
    FLAGS : edh_flags 
        port map (
            clk                 => clk,
            ce                  => ce,
            rst                 => rst,
            receive_mode        => receive_mode,
            ap_flag_word        => ap_flag_word,
            ff_flag_word        => ff_flag_word,
            anc_flag_word       => anc_flag_word,
            edh_missing         => edh_missing,
            edh_parity_err      => edh_parity_err,
            edh_format_err      => edh_format_err,
            rx_ap_crc_valid     => rx_ap_crc_valid,
            rx_ap_crc           => rx_ap_crc,
            rx_ff_crc_valid     => rx_ff_crc_valid,
            rx_ff_crc           => rx_ff_crc,
            rx_ap_flags         => in_ap_flags,
            rx_ff_flags         => in_ff_flags,
            rx_anc_flags        => in_anc_flags,
            anc_edh_local       => anc_edh_local,
            anc_idh_local       => anc_idh_local,
            anc_ues_local       => anc_ues_local,
            ap_idh_local        => ap_idh_local,
            ff_idh_local        => ff_idh_local,