anc_edh_processor.vhd

XAPP299 version 1.0 reference design files

signal dmux_anc_next:   std_ulogic;             -- anc_next output of anc_demux
signal dmux_edh_next:   std_ulogic;             -- edh_next output of anc_demux
signal dmux_edh_loc:    std_ulogic;             -- edh_loc output of anc_demux
signal mux_vid:         video_type;             -- video out of anc_mux
signal mux_trs:         std_ulogic;             -- trs output of anc_mux
signal mux_f:           std_ulogic;             -- f output of anc_mux
signal mux_v:           std_ulogic;             -- v output of anc_mux
signal mux_h:           std_ulogic;             -- h output of anc_mux
signal mux_hcnt:        hpos_type;              -- hcnt output of anc_mux
signal mux_vcnt:        vpos_type;              -- vcnt output of anc_mux
signal mux_sync_switch: std_ulogic;             -- sync_switch output of anc_mux
signal mux_eav_next:    std_ulogic;             -- eav_next output of anc_mux
signal mux_sav_next:    std_ulogic;             -- sav_next output of anc_mux
signal mux_xyz_word:    std_ulogic;             -- xyz_word output of anc_mux
signal mux_anc_next:    std_ulogic;             -- anc_next output of anc_mux
signal mux_edh_next:    std_ulogic;             -- edh_next output of anc_mux
signal mux_edh_loc:     std_ulogic;             -- edh_loc output of anc_mux
signal edh_all_flags :  edh_allflg_type;        -- flag vector for edh_errcnt module
signal anc_flags_int :  edh_flgset_type;        -- internal version of anc_flags output
signal ap_flags_int :   edh_flgset_type;        -- internal version of ap_flags output
signal ff_flags_int :   edh_flgset_type;        -- internal version of ff_flags output
signal VCC :            std_ulogic;		        -- pull-up

component video_decode
    port(
        clk:            in    std_ulogic;       -- clock input
        ce:             in    std_ulogic;       -- clock enable
        rst:            in    std_ulogic;       -- async reset input
        vid_in:         in    video_type;       -- input video
        reacquire:      in    std_ulogic;       -- forces autodetect to reacquire the standard
        en_sync_switch: in    std_ulogic;       -- enables sync switching
        en_trs_blank:   in    std_ulogic;       -- enables TRS blanking
        std:            inout vidstd_type;      -- video standard code
        std_locked:     inout std_ulogic;       -- autodetect circuit is locked to standard
        trs:            out   std_ulogic;       -- asserted during TRS symbol
        vid_out:        out   video_type;       -- output video stream
        field:          out   std_ulogic;       -- field indicator
        v_blank:        out   std_ulogic;       -- vertical blanking indicator
        h_blank:        out   std_ulogic;       -- horizontal blanking indicator
        horz_count:     out   hpos_type;        -- horizontal counter
        vert_count:     out   vpos_type;        -- vertical counter
        sync_switch:    out   std_ulogic;       -- asserted on sync switching lines
        locked:         out   std_ulogic;       -- asserted when flywheel is synced to input video
        eav_next:       out   std_ulogic;       -- next word is first word of EAV
        sav_next:       out   std_ulogic;       -- next word is first word of SAV
        xyz_word:       out   std_ulogic;       -- current word is the XYZ word
        anc_next:       out   std_ulogic;       -- next word is first word of ANC packet
        edh_next:       out   std_ulogic);      -- next word is first word of EDH packet
end component;

component edh_crc
    port (
        clk:            in  std_ulogic;         -- clock input
        ce:             in  std_ulogic;         -- clock enable
        rst:            in  std_ulogic;         -- async reset input
        f:              in  std_ulogic;         -- field bit
        h:              in  std_ulogic;         -- horizontal blanking bit
        eav_next:       in  std_ulogic;         -- asserted when next samplebegins EAV symbol
        xyz_word:       in  std_ulogic;         -- asserted when current word is the XYZ word of a TRS
        vid_in:         in  video_type;         -- video data
        vcnt:           in  vpos_type;          -- vertical line count
        std:            in  vidstd_type;        -- indicates the video standard
        locked:         in  std_ulogic;         -- asserted when flywheel is locked
        ap_crc:         out crc16_type;         -- calculated active picture CRC
        ap_crc_valid:   out std_ulogic;         -- asserted when AP CRC is valid
        ff_crc:         out crc16_type;         -- calculated full-frame CRC
        ff_crc_valid:   out std_ulogic);        -- asserted when FF CRC is valid
end component;

component edh_rx
    port (
        clk:            in  std_ulogic;         -- clock input
        ce:             in  std_ulogic;         -- clock enable
        rst:            in  std_ulogic;         -- async reset input
        rx_edh_next:    in  std_ulogic;         -- indicates the next word is the first word of a received EDH packet
        vid_in:         in  video_type;         -- video data
        edh_next:       in  std_ulogic;         -- EDH packet begins on next sample
        reg_flags:      in  std_ulogic;         -- 1 = register flag words, 0 = feed vid_in through
        ap_crc_valid:   out std_ulogic;         -- valid bit for active picture CRC
        ap_crc:         out crc16_type;         -- active picture CRC
        ff_crc_valid:   out std_ulogic;         -- valid bit for full field CRC
        ff_crc:         out crc16_type;         -- full field CRC
        edh_missing:    out std_ulogic;         -- asserted when last expected EDH packet was missing
        edh_parity_err: out std_ulogic;         -- asserted when a parity error occurs in EDH packet
        edh_chksum_err: out std_ulogic;         -- asserted when a checksum error occurs in EDH packet
        edh_format_err: out std_ulogic;         -- asserted when a format error is found in EDH packet
        in_ap_flags:    out edh_flgset_type;    -- received AP flag word to edh_flags module
        in_ff_flags:    out edh_flgset_type;    -- received FF flag word to edh_flags module
        in_anc_flags:   out edh_flgset_type;    -- received ANC flag word to edh_flags module
        rx_ap_flags:    out edh_flgset_type;    -- received & registered AP flags for external inspection
        rx_ff_flags:    out edh_flgset_type;    -- received & registered FF flags for external inspection
        rx_anc_flags:   out edh_flgset_type);   -- received & registered ANC flags for external inspection
end component;

component edh_loc
    port (
        clk:            in  std_ulogic;         -- clock input
        ce:             in  std_ulogic;         -- clock enable
        rst:            in  std_ulogic;         -- async reset input
        f:              in  std_ulogic;         -- field bit
        vcnt:           in  vpos_type;          -- vertical line count
        hcnt:           in  hpos_type;          -- horizontal position
        std:            in  vidstd_type;        -- video standards
        edh_next:       out std_ulogic);        -- EDH packet should begin on next sample
end component;

component anc_rx
    port (
        clk:            in  std_ulogic;         -- clock input
        ce:             in  std_ulogic;         -- clock enable
        rst:            in  std_ulogic;         -- async reset input
        locked:         in  std_ulogic;         -- video decoder locked signal
        rx_anc_next:    in  std_ulogic;         -- asserted when next word begins ANC packet
        rx_edh_next:    in  std_ulogic;         -- asserted when next word begins EDH packet
        edh_packet:     in  std_ulogic;         -- indicates an EDH packet is being generated
        vid_in:         in  video_type;         -- video input data
        anc_edh_local:  out std_ulogic);        -- ANC error detected here flag
end component;

component edh_flags
    port (
        clk:                in  std_ulogic;     -- clock input
        ce:                 in  std_ulogic;     -- clock enable
        rst:                in  std_ulogic;     -- async reset input
        receive_mode:       in  std_ulogic;     -- asserted if receiver is active
        ap_flag_word:       in  std_ulogic;     -- selects the AP flag word for flag_bus
        ff_flag_word:       in  std_ulogic;     -- selects the FF flag word for flag_bus
        anc_flag_word:      in  std_ulogic;     -- selects the ANC flag word for the flag_bus
        edh_missing:        in  std_ulogic;     -- EDH packet missing from data stream
        edh_parity_err:     in  std_ulogic;     -- EDH packet parity error
        edh_format_err:     in  std_ulogic;     -- EDH packet format error
        rx_ap_crc_valid:    in  std_ulogic;     -- received AP CRC valid bit
        rx_ap_crc:          in  crc16_type;     -- received AP CRC value 
        rx_ff_crc_valid:    in  std_ulogic;     -- received FF CRC valid bit
        rx_ff_crc:          in  crc16_type;     -- received FF CRC value
        rx_ap_flags:        in  edh_flgset_type;-- received AP flag word
        rx_ff_flags:        in  edh_flgset_type;-- received FF flag word
        rx_anc_flags:       in  edh_flgset_type;-- recevied ANC flag word
        anc_edh_local:      in  std_ulogic;     -- local ANC EDH flag input
        anc_idh_local:      in  std_ulogic;     -- local ANC IDH flag input
        anc_ues_local:      in  std_ulogic;     -- local ANC UES flag input
        ap_idh_local:       in  std_ulogic;     -- local AP IDH flag input
        ff_idh_local:       in  std_ulogic;     -- local FF IDH flag input
        calc_ap_crc_valid:  in  std_ulogic;     -- calculated AP CRC valid bit
        calc_ap_crc:        in  crc16_type;     -- calculated AP CRC value
        calc_ff_crc_valid:  in  std_ulogic;     -- calculated FF CRC value
        calc_ff_crc:        in  crc16_type;     -- calculated FF CRC
        flags:              out edh_flgset_type;-- flag bus output
        ap_flags:           out edh_flgset_type;-- AP flags from last EDH packet sent
        ff_flags:           out edh_flgset_type;-- FF flags from last EDH packet sent
        anc_flags:          out edh_flgset_type);-- ANC flags from last EDH packet sent
end component;

component edh_errcnt
    port (
        clk:            in    std_ulogic;       -- clock input
        ce:             in    std_ulogic;       -- clock enable
        rst:            in    std_ulogic;       -- async reset input
        clr_errcnt:     in    std_ulogic;       -- clears the error counter
        count_en:       in    std_ulogic;       -- enables error counter when high
        flag_enables:   in    edh_allflg_type;  -- specifies which error flags cause the counter to increment
        flags:          in    edh_allflg_type;  -- error flag inputs
        edh_next:       in    std_ulogic;       -- counter increment on edh_next asserted
        errcnt:         out   edh_errcnt_type); -- errored field counter
end component;

component anc_demux
    port (
        clk:            in    std_ulogic;       -- clock input
        ce:             in    std_ulogic;       -- clock enable
        rst:            in    std_ulogic;       -- async reset input
        vid_in:         in    video_type;       -- video data input
        en_a:           in    std_ulogic;       -- enable for DID A decoder
        did_a:          in    ubyte_type;       -- first DID code to match
        sdid_a:         in    ubyte_type;       -- first SDID code to match
        del_pkt_a:      in    std_ulogic;       -- packet will be deleted if asserted
        en_b:           in    std_ulogic;       -- enable for DID B decoder
        did_b:          in    ubyte_type;       -- second DID code to match
        sdid_b:         in    ubyte_type;       -- second SDID code to match
        del_pkt_b:      in    std_ulogic;       -- packet will be deleted if asserted
        en_c:           in    std_ulogic;       -- enable for DID C decoder
        did_c:          in    ubyte_type;       -- third DID code to match
        sdid_c:         in    ubyte_type;       -- third SDID code to match
        del_pkt_c:      in    std_ulogic;       -- packet will be deleted if asserted
        en_d:           in    std_ulogic;       -- enable for DID D decoder
        did_d:          in    ubyte_type;       -- fourth DID code to match
        sdid_d:         in    ubyte_type;       -- fourth SDID code to match
        del_pkt_d:      in    std_ulogic;       -- packet will be deleted if asserted
        in_trs:         in    std_ulogic;       -- asserted during the four words of all TRS symbols
        in_f:           in    std_ulogic;       -- field indicator
        in_v:           in    std_ulogic;       -- vertical blanking indicator
        in_h:           in    std_ulogic;       -- horizontal blanking indicator
        in_hcnt:        in    hpos_type;        -- horizontal position
        in_vcnt:        in    vpos_type;        -- vertical position
        in_sync_switch: in    std_ulogic;       -- synchronous switching line indicator
        in_eav_next:    in    std_ulogic;       -- next word begins an EAV
        in_sav_next:    in    std_ulogic;       -- next word begins an SAV
        in_xyz_word:    in    std_ulogic;       -- current word is a TRS XYZ word
        in_anc_next:    in    std_ulogic;       -- asserted when next word begins received ANC packet
        in_edh_next:    in    std_ulogic;       -- asserted when next word begins received EDH packet
        in_edh_loc:     in    std_ulogic;       -- asserted when next word is starting location where EDH
        data_out:       out   video_type;       -- output packet data
        data_out_valid: out   std_ulogic;       -- asserted while all words of a matching packet are on data_out
        match_code:     out                     -- indicates DID/SDID combination matched the current packet
            std_ulogic_vector(1 downto 0);  
        did:            out   std_ulogic;       -- asserted when a DID word from a matching packet is on data_out
        dbn:            out   std_ulogic;       -- asserted when a DBN word from a matching packet is on data_out
        sdid:           out   std_ulogic;       -- asserted when an SDID word from a matching packet is on data_out
        dc:             out   std_ulogic;       -- asserted when a DC word from a matching packet is on data_out
        udw:            out   std_ulogic;       -- asserted when a UDW word from a matching packet is on data_out
        cs:             out   std_ulogic;       -- asserted when a CS word from a matching packet is on data_out
        vid_out:        out   video_type;       -- output video stream
        out_trs:        out   std_ulogic;       -- delayed version of in_trs
        out_f:          out   std_ulogic;       -- delayed version of in_f
        out_v:          out   std_ulogic;       -- delayed version of in_v
        out_h:          out   std_ulogic;       -- delayed version of in_h
        out_hcnt:       out   hpos_type;        -- delayed version of in_hcnt
        out_vcnt:       out   vpos_type;        -- delayed version of in_vcnt
        out_sync_switch:out   std_ulogic;       -- delayed version of in_sync_switch
        out_eav_next:   out   std_ulogic;       -- delayed version of in_eav_next
        out_sav_next:   out   std_ulogic;       -- delayed version of in_sav_next
        out_xyz_word:   out   std_ulogic;       -- delayed version of in_xyz_word
        out_anc_next:   out   std_ulogic;       -- delayed version of in_anc_next
        out_edh_next:   out   std_ulogic;       -- delayed version of in_edh_next
        out_edh_loc:    out   std_ulogic);      -- delayed version of in_edh_loc
end component;

component anc_mux
    port (
        clk:            in    std_ulogic;       -- clock input
        ce:             in    std_ulogic;       -- clock enable
        rst:            in    std_ulogic;       -- async reset input
        vid_in:         in    video_type;       -- video data input
        std:            in    vidstd_type;      -- current video standard
        hanc_pkt:       in    std_ulogic;       -- ANC packet to be sent can be inserted into HANC space
        vanc_pkt:       in    std_ulogic;       -- ANC packet to be sent can be inserted into VANC space
        pkt_rdy_in:     in    std_ulogic;       -- indicates packet has been loaded into input regs
        calc_udw_parity:in    std_ulogic;       -- indicates that module should calculate parity on UDW
        data_in:        in    video_type;       -- input data bus
        ld_did:         in    std_ulogic;       -- load DID register
        ld_dbn:         in    std_ulogic;       -- load SDID/DBN register