edh_rx.vhd

XAPP299 version 1.0 reference design files

--------------------------------------------------------------------------------
-- edh_rx.vhd
--
-- SDI EDH packet receiver
--
--
--
--                  Author: John F. Snow
--                  Staff Applications Engineer
--
--                  Video Applications
--                  Advanced Products Group
--                  Xilinx, Inc.
--
--                  Copyright (c) 2002 Xilinx, Inc.
--                  All rights reserved
--
--                  Date:   May 8, 2002
--
--                  RESTRICTED RIGHTS LEGEND
--
--      This software has not been published by the author, and 
--      has been disclosed to others for the purpose of enhancing 
--      and promoting design productivity in Xilinx products.
--
--      Therefore use, duplication or disclosure, now and in the 
--      future should give consideration to the productivity 
--      enhancements afforded the user of this code by the author's 
--      efforts.  Thank you for using our products !
--
-- Disclaimer:  THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY 
--              WHATSOEVER AND XILINX SPECIFICALLY DISCLAIMS ANY 
--              IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
--              A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
--
-- Revision:
--              May 8, 2002     Release
--
-- Other modules instanced in this design:
--          none
--
--------------------------------------------------------------------------------
-- 
-- This module processes a received EDH packet. It examines the vcnt and hcnt
-- values from the video flywheel to determine when an EDH packet should occur. 
-- If there is no EDH packet then, the missing EDH packet flag is asserted. If 
-- an EDH packet occurs somewhere other than where it is expected, the misplaced
-- EDH packet flag is asserted.
-- 
-- When an EDH packet at the expected location if found, it is checked to make
-- sure all the words of the packet are correct, that the parity of the payload
-- data words are correct, and that the checksum for the packet is correct.
-- 
-- The active picture and full field CRCs and flags are extracted and stored in
-- registers.
--

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;

use work.anc_edh_pkg.all;

entity edh_rx is
    port (
        clk:            in  std_ulogic;     -- clock input
        ce:             in  std_ulogic;     -- clock enable
        rst:            in  std_ulogic;     -- async reset input
        rx_edh_next:    in  std_ulogic;     -- indicates the next word is the first word of a received EDH packet
        vid_in:         in  video_type;     -- video data
        edh_next:       in  std_ulogic;     -- EDH packet begins on next sample
        reg_flags:      in  std_ulogic;     -- 1 = register flag words, 0 = feed vid_in through

        -- outputs
        ap_crc_valid:   out std_ulogic;     -- valid bit for active picture CRC
        ap_crc:         out crc16_type;     -- active picture CRC
        ff_crc_valid:   out std_ulogic;     -- valid bit for full field CRC
        ff_crc:         out crc16_type;     -- full field CRC
        edh_missing:    out std_ulogic;     -- asserted when last expected EDH packet was missing
        edh_parity_err: out std_ulogic;     -- asserted when a parity error occurs in EDH packet
        edh_chksum_err: out std_ulogic;     -- asserted when a checksum error occurs in EDH packet
        edh_format_err: out std_ulogic;     -- asserted when a format error is found in EDH packet
        in_ap_flags:    out edh_flgset_type;-- received AP flag word to edh_flags module
        in_ff_flags:    out edh_flgset_type;-- received FF flag word to edh_flags module
        in_anc_flags:   out edh_flgset_type;-- received ANC flag word to edh_flags module
        rx_ap_flags:    out edh_flgset_type;-- received & registered AP flags for external inspection
        rx_ff_flags:    out edh_flgset_type;-- received & registered FF flags for external inspection
        rx_anc_flags:   out edh_flgset_type);-- received & registered ANC flags for external inspection
end;        

architecture synth of edh_rx is

-------------------------------------------------------------------------------
-- Constant definitions
--      

--
-- This group of constants defines the fixed values of some of the words in
-- the EDH packet.
--
constant EDH_DID :      video_type := "0111110100"; --h1f4;
constant EDH_DBN :      video_type := "1000000000"; --h200;
constant EDH_DC  :      video_type := "0100010000"; --h110;

--
-- This group of constants defines the states of the EDH processor state
-- machine.
--
constant STATE_WIDTH :  integer := 5;
subtype state_type is std_ulogic_vector(STATE_WIDTH - 1 downto 0);

constant S_WAIT     : state_type := "00000";
constant S_ADF1     : state_type := "00001";
constant S_ADF2     : state_type := "00010";
constant S_ADF3     : state_type := "00011";
constant S_DID      : state_type := "00100";
constant S_DBN      : state_type := "00101";
constant S_DC       : state_type := "00110";
constant S_AP1      : state_type := "00111";
constant S_AP2      : state_type := "01000";
constant S_AP3      : state_type := "01001";
constant S_FF1      : state_type := "01010";
constant S_FF2      : state_type := "01011";
constant S_FF3      : state_type := "01100";
constant S_ANCFLG   : state_type := "01101";
constant S_APFLG    : state_type := "01110";
constant S_FFFLG    : state_type := "01111";
constant S_RSV1     : state_type := "10000";
constant S_RSV2     : state_type := "10001";
constant S_RSV3     : state_type := "10010";
constant S_RSV4     : state_type := "10011";
constant S_RSV5     : state_type := "10100";
constant S_RSV6     : state_type := "10101";
constant S_RSV7     : state_type := "10110";
constant S_CHK      : state_type := "10111";
constant S_ERRM     : state_type := "11000";  -- Missing EDH packet
constant S_ERRF     : state_type := "11001";  -- Format error in EDH packet
constant S_ERRC     : state_type := "11010";  -- Checksum error in EDH packet

-------------------------------------------------------------------------------
-- Signal definitions
--
signal current_state:   state_type;         -- FSM current state
signal next_state:      state_type;         -- FSM next state
signal parity_err:      std_ulogic;         -- detects parity errors on EDH words
signal parity:          std_ulogic;         -- used to generate parity_err
signal checksum:        cksum_type;         -- checksum for EDH packet
signal ld_ap1:          std_ulogic;         -- loads bits 5:0 of active picture crc
signal ld_ap2:          std_ulogic;         -- loads bits 11:6 of active picture crc
signal ld_ap3:          std_ulogic;         -- loads bits 15:12 of active picture crc
signal ld_ff1:          std_ulogic;         -- loads bits 5:0 of full field crc
signal ld_ff2:          std_ulogic;         -- loads bits 11:6 of full field crc
signal ld_ff3:          std_ulogic;         -- loads bits 15:12 of full field crc
signal ld_ap_flags:     std_ulogic;         -- loads the rx_ap_flags register
signal ld_ff_flags:     std_ulogic;         -- loads the rx_ff_flags register
signal ld_anc_flags:    std_ulogic;         -- loads the rx_anc_flags register
signal clr_checksum:    std_ulogic;         -- asserted to clear the checksum
signal clr_errors:      std_ulogic;         -- asserted to clear the EDH packet errs
signal ap_crc_reg:      crc16_type;         -- active picture CRC register
signal ff_crc_reg:      crc16_type;         -- full field CRC register                  
signal missing_err:     std_ulogic;         -- asserted when EDH packet is missing
signal format_err:      std_ulogic;         -- asserted when format error in EDH packet is detected
signal check_parity:    std_ulogic;         -- asserted when parity error in EDH packet is detected
signal checksum_err:    std_ulogic;         -- asserted when checksum error in EDH packet is detected
signal rx_edh:          std_ulogic;         -- asserted when current word is first word of received EDH
signal rx_ap_flg_reg:   edh_flgset_type;    -- holds the received AP flags
signal rx_ff_flg_reg:   edh_flgset_type;    -- holds the received FF flags
signal rx_anc_flg_reg:  edh_flgset_type;    -- holds the received ANC flags

begin
    
    --
    -- delay flip-flop for rx_edh_next
    --
    -- The resulting signal, rx_edh, is asserted during the first word of a
    -- received EDH packet.
    --
    process(clk, rst)
    begin
        if (rst = '1') then
            rx_edh <= '0';
        elsif (clk'event and clk = '1') then
            if (ce = '1') then
                rx_edh <= rx_edh_next;
            end if;
        end if;
    end process;

    --
    -- FSM: current_state register
    --
    -- This code implements the current state register. 
    --
    process(clk, rst)
    begin
        if (rst = '1') then
            current_state <= S_WAIT;
        elsif (clk'event and clk = '1') then
            if (ce = '1') then
                current_state <= next_state;
            end if;
        end if;
    end process;

    --
    -- FSM: next_state logic
    --
    -- This case statement generates the next_state value for the FSM based on
    -- the current_state and the various FSM inputs.
    --
    process(current_state, edh_next, rx_edh, vid_in, parity_err, checksum)
    begin
        case current_state is
      
            when S_WAIT =>
                if (edh_next = '1') then
                    next_state <= S_ADF1;
                else
                    next_state <= S_WAIT;
                end if;

            when S_ADF1 =>
                if (rx_edh = '1') then
                    next_state <= S_ADF2;
                else
                    next_state <= S_ERRM;
                end if;

            when S_ADF2 =>
                next_state <= S_ADF3;

            when S_ADF3 =>
                next_state <= S_DID;

            when S_DID =>
                next_state <= S_DBN;

            when S_DBN =>
                if (vid_in(9 downto 2) = EDH_DBN(9 downto 2)) then
                    next_state <= S_DC;
                else
                    next_state <= S_ERRF;
                end if;

            when S_DC =>
                if (vid_in(9 downto 0) = EDH_DC(9 downto 0)) then
                    next_state <= S_AP1;
                else
                    next_state <= S_ERRF;
                end if;

            when S_AP1 =>
                next_state <= S_AP2;

            when S_AP2 =>
                next_state <= S_AP3;

            when S_AP3 =>
                next_state <= S_FF1;

            when S_FF1 =>
                next_state <= S_FF2;

            when S_FF2 =>
                next_state <= S_FF3;

            when S_FF3 =>
                next_state <= S_ANCFLG;

            when S_ANCFLG =>    
                next_state <= S_APFLG;

            when S_APFLG => 
                next_state <= S_FFFLG;
                        
            when S_FFFLG => 
                next_state <= S_RSV1;

            when S_RSV1 =>
                next_state <= S_RSV2;

            when S_RSV2 =>
                next_state <= S_RSV3;

            when S_RSV3 =>
                next_state <= S_RSV4;

            when S_RSV4 =>
                next_state <= S_RSV5;

            when S_RSV5 =>
                next_state <= S_RSV6;