📄 test_anc_demux.vhd
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variable temp_hpos : std_logic_vector(11 downto 0);
begin
if (clk'event and clk = '0') then
vid_in <= d;
if (replace = '1') then
if (hcnt = ins_start) then
vid_in <= ADF0;
elsif (hcnt = ins_start + 1 or hcnt = ins_start + 2) then
vid_in <= ADF1;
elsif (hcnt = ins_start + DID_WORD) then
vid_in <= pad2_10(ins_did);
checksum <= pad2_9(ins_did);
elsif (hcnt = ins_start + DBN_WORD) then
vid_in <= pad2_10(ins_sdid);
checksum <= cksum_type(std_logic_vector(checksum) + std_logic_vector(pad2_9(ins_sdid)));
elsif (hcnt = ins_start + DC_WORD) then
vid_in <= pad2_10(ins_dc);
checksum <= cksum_type(std_logic_vector(checksum) + std_logic_vector(pad2_9(ins_dc)));
elsif (hcnt > ins_start + DC_WORD and
hcnt <= ins_start + DC_WORD + std_logic_vector(ins_dc)) then
temp_hpos := std_logic_vector(hcnt - (ins_start + DC_WORD));
vid_in <= video_type(temp_hpos(9 downto 0) or "1000000000");
checksum <= cksum_type(std_logic_vector(checksum) + temp_hpos(8 downto 0));
elsif (hcnt = ins_start + DC_WORD + std_logic_vector(ins_dc) + 1) then
vid_in <= (not checksum(8) & checksum);
else
vid_in <= d;
end if;
end if;
end if;
end process;
--
-- This statement stops the simulation when the vcnt value reaches the end of
-- the simulation.
--
process
variable l : line;
variable success_string : string (1 to 36)
:= "Test completed with no errors found.";
variable error_string : string (1 to 27)
:= "Test completed with errors.";
begin
wait until (locked'event and locked = '1');
wait until (vcnt = START_LINE + 5);
if (error_found) then
write(l, error_string);
writeline(output, l);
else
write(l, success_string);
writeline(output, l);
end if;
enclk <= '0';
wait;
end process;
-- Generate the expected data
process(vcnt)
begin
if (vcnt = START_LINE) then
match_code <= "00";
type_code <= 1;
elsif (vcnt = START_LINE_PLUS_1) then
match_code <= "00";
type_code <= 2;
elsif (vcnt = START_LINE_PLUS_2) then
match_code <= "01";
type_code <= 2;
elsif (vcnt = START_LINE_PLUS_3) then
match_code <= "10";
type_code <= 2;
elsif (vcnt = START_LINE_PLUS_4) then
match_code <= "11";
type_code <= 2;
else
match_code <= "00";
type_code <= 0;
end if;
end process;
process(clk)
begin
if (clk'event and clk = '0') then
expected_vid <= dly_vid(LATENCY-1);
expected_anc <= dly_vid(LATENCY-2);
expected_did <= '0';
expected_dbn <= '0';
expected_sdid <= '0';
expected_dc <= '0';
expected_udw <= '0';
expected_cs <= '0';
expected_valid <= '0';
expected_match <= "00";
if (locked = '1') then
if (vcnt >= START_LINE and vcnt < START_LINE + 5) then
if (hcnt = FIRST_FREE + DID_WORD + LATENCY - 1) then
expected_match <= match_code;
expected_did <= '1';
expected_valid <= '1';
end if;
if (hcnt = FIRST_FREE + DBN_WORD + LATENCY - 1) then
expected_match <= match_code;
if (type_code = 1) then
expected_dbn <= '1';
else
expected_sdid <= '1';
end if;
expected_valid <= '1';
if (vcnt = START_LINE_PLUS_4) then
expected_vid <= video_type(TO_UNSIGNED(16#180#, video_type'length));
end if;
end if;
if (hcnt = FIRST_FREE + DC_WORD + LATENCY - 1) then
expected_match <= match_code;
expected_dc <= '1';
expected_valid <= '1';
end if;
if (hcnt >= FIRST_FREE + DC_WORD + LATENCY and
hcnt <= FIRST_FREE + DC_WORD + std_logic_vector(INSERT_DC) + LATENCY - 1) then
expected_match <= match_code;
expected_udw <= '1';
expected_valid <= '1';
end if;
if (hcnt = FIRST_FREE + DC_WORD + std_logic_vector(INSERT_DC) + LATENCY) then
expected_match <= match_code;
expected_cs <= '1';
expected_valid <= '1';
end if;
if (hcnt = FIRST_FREE + DC_WORD + std_logic_vector(INSERT_DC) + LATENCY + 1) then
if (vcnt = START_LINE_PLUS_4) then
expected_vid <= video_type(TO_UNSIGNED(16#1ec#, video_type'length));
end if;
end if;
end if;
end if;
end if;
end process;
--
-- Delay the vid_in value by the amount of latency in the anc_edh_processor
-- module. The delayed video is used as a reference to verify that the video
-- out of the module is correct.
--
process(clk, rst)
begin
if (rst = '1') then
for k in 0 to LATENCY - 1 loop
dly_vid(k) <= (others => '0');
end loop;
elsif (clk'event and clk = '1') then
for k in 0 to LATENCY - 2 loop
dly_vid(k+1) <= dly_vid(k);
end loop;
dly_vid(0) <= vid_in;
end if;
end process;
--
-- Compare expected with video out of processor except during the EDH packet.
-- The EDH packet will not match the input EDH packet value due to EDH
-- packet processing.
--
process(clk)
variable l : line;
variable exp_str : string (1 to 12) := " expected = ";
variable vid_out_str : string (1 to 17) := "Error: vid_out = ";
variable anc_out_str : string (1 to 17) := "Error: anc_out = ";
variable match_str : string (1 to 19) := "Error: anc_match = ";
variable did_str : string (1 to 13) := "Error: did = ";
variable dbn_str : string (1 to 13) := "Error: dbn = ";
variable sdid_str : string (1 to 14) := "Error: sdid = ";
variable dc_str : string (1 to 12) := "Error: dc = ";
variable udw_str : string (1 to 13) := "Error: udw = ";
variable cs_str : string (1 to 12) := "Error: cs = ";
variable valid_str : string (1 to 52) := "Error: anc_out_valid was expected to be 1, but was 0";
variable temp_byte : std_logic_vector(3 downto 0);
begin
if (clk'event and clk = '1') then
if (locked = '1' and edh_packet = '0') then
if (expected_vid /= vid_out) then
write(l, vid_out_str);
hwrite(l, ("00" & vid_out), left, vid_out'length + 2);
write(l, exp_str);
hwrite(l, ("00" & expected_vid), left, expected_vid'left + 2);
writeline(output, l);
error_found <= true;
end if;
if (expected_anc /= anc_out) then
write(l, anc_out_str);
hwrite(l, ("00" & anc_out), left, anc_out'length + 2);
write(l, exp_str);
hwrite(l, ("00" & expected_anc), left, expected_anc'left + 2);
writeline(output, l);
error_found <= true;
end if;
if (expected_valid = '1') then
if (anc_out_valid = '0') then
write(l, valid_str);
writeline(output, l);
error_found <= true;
end if;
if (anc_match /= expected_match) then
write(l, match_str);
hwrite(l, ("00" & anc_match), left, 4);
write(l, exp_str);
hwrite(l, ("00" & expected_match), left, 4);
writeline(output, l);
error_found <= true;
end if;
if (did /= expected_did) then
write(l, did_str);
temp_byte := "000" & did;
hwrite(l, temp_byte, left, 4);
write(l, exp_str);
temp_byte := "000" & expected_did;
hwrite(l, temp_byte, left, 4);
writeline(output, l);
error_found <= true;
end if;
if (dbn /= expected_dbn) then
write(l, dbn_str);
temp_byte := "000" & dbn;
hwrite(l, temp_byte, left, 4);
write(l, exp_str);
temp_byte := "000" & expected_dbn;
hwrite(l, temp_byte, left, 4);
writeline(output, l);
error_found <= true;
end if;
if (sdid /= expected_sdid) then
write(l, sdid_str);
temp_byte := "000" & sdid;
hwrite(l, temp_byte, left, 4);
write(l, exp_str);
temp_byte := "000" & expected_sdid;
hwrite(l, temp_byte, left, 4);
writeline(output, l);
error_found <= true;
end if;
if (dc /= expected_dc) then
write(l, dc_str);
temp_byte := "000" & dc;
hwrite(l, temp_byte, left, 4);
write(l, exp_str);
temp_byte := "000" & expected_dc;
hwrite(l, temp_byte, left, 4);
writeline(output, l);
error_found <= true;
end if;
if (udw /= expected_udw) then
write(l, udw_str);
temp_byte := "000" & udw;
hwrite(l, temp_byte, left, 4);
write(l, exp_str);
temp_byte := "000" & expected_udw;
hwrite(l, temp_byte, left, 4);
writeline(output, l);
error_found <= true;
end if;
if (cs /= expected_cs) then
write(l, cs_str);
temp_byte := "000" & cs;
hwrite(l, temp_byte, left, 4);
write(l, exp_str);
temp_byte := "000" & expected_cs;
hwrite(l, temp_byte, left, 4);
writeline(output, l);
error_found <= true;
end if;
end if;
end if;
end if;
end process;
end sim;⌨️ 快捷键说明
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