📄 test_anc_demux.vhd
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rx_anc_flags: out edh_flgset_type;-- ANC error flags freceived from last EDH packet
ap_flags: out edh_flgset_type;-- transmitted AP error flags from last field
ff_flags: out edh_flgset_type;-- transmitted FF error flags from last field
anc_flags: out edh_flgset_type;-- transmitted ANC error flags from last field
packet_flags: out edh_pktflg_type;-- error flags related to the received packet processing
errcnt: out edh_errcnt_type;-- errored fields counter
edh_packet: out std_ulogic; -- asserted during all words of a generated EDH packet
-- ANC demux outputs
anc_out: out video_type; -- output packet data
anc_out_valid: out std_ulogic; -- asserted while all words of a matching packet are on anc_out
anc_match: out -- indicates DID/SDID combination matched the current packet
std_ulogic_vector(1 downto 0);
did: out std_ulogic; -- asserted when a DID word from a matching packet is on anc_out
dbn: out std_ulogic; -- asserted when a DBN word from a matching packet is on anc_out
sdid: out std_ulogic; -- asserted when an SDID word from a matching packet is on anc_out
dc: out std_ulogic; -- asserted when a DC word from a matching packet is on anc_out
udw: out std_ulogic; -- asserted when a UDW word from a matching packet is on anc_out
cs: out std_ulogic; -- asserted when a CS word from a matching packet is on anc_out
-- ANC mux outputs
pkt_in_empty: out std_ulogic); -- module is ready for input packet to be loaded
end component;
--
-- pad2_10 function
--
-- This function takes an 8-bit value, computes a parity bit, then creates a
-- 10-bit word with the complement of the parity bit in bit 9 and the parity
-- bit in bit 8, followed by the original 8-bit value.
--
function pad2_10(d: ubyte_type) return video_type is
variable parity : std_ulogic;
begin
parity := d(7) xor d(6) xor d(5) xor d(4) xor d(3) xor d(2) xor d(1) xor d(0);
return(not parity & parity & d);
end pad2_10;
--
-- pad2_9 function
--
-- This function takes an 8-bit value, computes a parity bit, then creates a
-- 9-bit word with the parity bit in bit 8, followed by the original 8-bit
-- value.
--
function pad2_9(d: ubyte_type) return cksum_type is
variable parity : std_ulogic;
begin
parity := d(7) xor d(6) xor d(5) xor d(4) xor d(3) xor d(2) xor d(1) xor d(0);
return(parity & d);
end pad2_9;
begin
--
-- Instantiate the ANC/EDH processor module
--
U1 : anc_edh_processor
port map (
clk => clk,
ce => rx_ce,
rst => rst,
vid_in => vid_in,
reacquire => GND,
en_sync_switch => VCC,
en_trs_blank => VCC,
anc_idh_local => anc_idh_local,
anc_ues_local => anc_ues_local,
ap_idh_local => ap_idh_local,
ff_idh_local => ff_idh_local,
errcnt_flg_en => errcnt_flg_en,
clr_errcnt => GND,
receive_mode => VCC,
en_a => en_a,
did_a => did_a,
sdid_a => sdid_a,
del_pkt_a => del_pkt_a,
en_b => en_b,
did_b => did_b,
sdid_b => sdid_b,
del_pkt_b => del_pkt_b,
en_c => en_c,
did_c => did_c,
sdid_c => sdid_c,
del_pkt_c => del_pkt_c,
en_d => en_d,
did_d => did_d,
sdid_d => sdid_d,
del_pkt_d => del_pkt_d,
hanc_pkt => GND,
vanc_pkt => GND,
pkt_rdy_in => GND,
calc_udw_parity => GND,
anc_in => GND10,
ld_did => GND,
ld_dbn => GND,
ld_dc => GND,
ld_udw => GND,
udw_wr_adr => GND8,
vid_out => vid_out,
std => std,
std_locked => std_locked,
trs => trs,
field => f,
v_blank => v,
h_blank => h,
horz_count => hcnt,
vert_count => vcnt,
sync_switch => sync_switch,
locked => locked,
eav_next => eav_next,
sav_next => sav_next,
xyz_word => xyz_word,
anc_next => anc_next,
edh_next => edh_next,
rx_ap_flags => rx_ap_flags,
rx_ff_flags => rx_ff_flags,
rx_anc_flags => rx_anc_flags,
ap_flags => ap_flags,
ff_flags => ff_flags,
anc_flags => anc_flags,
packet_flags => packet_flags,
errcnt => errcnt,
edh_packet => edh_packet,
anc_out => anc_out,
anc_out_valid => anc_out_valid,
anc_match => anc_match,
did => did,
dbn => dbn,
sdid => sdid,
dc => dc,
udw => udw,
cs => cs,
pkt_in_empty => open);
edh_format_err <= packet_flags(3);
edh_chksum_err <= packet_flags(2);
edh_parity_err <= packet_flags(1);
edh_missing <= packet_flags(0);
--
-- Read in one frame of NTSC video into memory array
--
process
file infile: TEXT open read_mode is "C:/work/XAPP299/sim/one_frame.txt";
variable buf: line;
variable data: std_logic_vector(11 downto 0);
variable words: integer := 0;
variable good: boolean;
begin
while not (endfile(infile)) loop
readline(infile, buf); -- read a line from file into buffer
for i in 0 to 15 loop -- there are 16 words per line in the file
exit when words = MAX_MEM; -- last line doesn't contain 16 words so put an early escape mechanism here
hread(buf, data, good); -- read one word from the buffer
assert good -- make sure the read was OK
report "Text I/O read error"
severity failure;
memory(words) := video_type(data(9 downto 0)); -- write word to the memory array
words := words + 1;
end loop;
end loop;
wait;
end process;
--
-- Generate a clock signal at 27 MHz.
--
clk <= enclk and not clk after 18.5 ns;
rx_ce <= '1';
--
-- Assert the reset signal for the first few clock cycles
--
process
begin
for count in 1 to 5 loop
wait until clk'event and clk = '0';
end loop;
rst <= '0';
wait;
end process;
--
-- This code generates the index into the memory array and the frame counter.
-- The index begins at a negative number. When the index is negative, no video
-- is generated. A few cycles with no video are used to make sure the modules
-- come out of reset before the test set is sent. When the index reaches the
-- maximum size of the memory array, it is reset to zero and the frame counter
-- is incremented.
--
process(clk, rst)
begin
if (rst = '1') then
i <= -5;
frames <= 0;
elsif (clk'event and clk = '1') then
if (i = MAX_MEM - 1 and frames < 8) then
i <= 0;
frames <= frames + 1;
else
i <= i + 1;
end if;
end if;
end process;
--
-- Whenever the memory index changes, look up a new video data value from the
-- memory array and assign that value to d.
--
process(i)
begin
if (i < 0 or i >= MAX_MEM or frames > 7) then
d <= (others => '0');
else
d <= memory(i);
end if;
end process;
--
-- This code initializes the DID/SDID input pairs to the processor.
--
process
begin
en_a <= '1';
did_a <= INSERT_DID_TYPE1;
sdid_a <= INSERT_SDID1;
del_pkt_a <= '0';
en_b <= '1';
did_b <= INSERT_DID_TYPE2;
sdid_b <= INSERT_SDID2;
del_pkt_b <= '0';
en_c <= '1';
did_c <= INSERT_DID_TYPE2;
sdid_c <= INSERT_SDID3;
del_pkt_c <= '0';
en_d <= '1';
did_d <= INSERT_DID_TYPE2;
sdid_d <= INSERT_SDID4;
del_pkt_d <= '1';
wait until (locked'event and locked = '1');
wait until (vcnt = START_LINE + 1);
wait until (clk'event and clk = '0');
did_a <= INSERT_DID_TYPE2;
wait;
end process;
--
-- This code generates various values for the inserted ANC packet.
--
process(vcnt)
begin
case vcnt is
when START_LINE =>
replace <= locked;
ins_start <= FIRST_FREE;
ins_did <= INSERT_DID_TYPE1;
ins_sdid <= ubyte_type(TO_UNSIGNED(16#40#, ubyte_type'length));
ins_dc <= INSERT_DC;
when START_LINE_PLUS_1 =>
replace <= locked;
ins_start <= FIRST_FREE;
ins_did <= INSERT_DID_TYPE2;
ins_sdid <= INSERT_SDID1;
ins_dc <= INSERT_DC;
when START_LINE_PLUS_2 =>
replace <= locked;
ins_start <= FIRST_FREE;
ins_did <= INSERT_DID_TYPE2;
ins_sdid <= INSERT_SDID2;
ins_dc <= INSERT_DC;
when START_LINE_PLUS_3 =>
replace <= locked;
ins_start <= FIRST_FREE;
ins_did <= INSERT_DID_TYPE2;
ins_sdid <= INSERT_SDID3;
ins_dc <= INSERT_DC;
when START_LINE_PLUS_4 =>
replace <= locked;
ins_start <= FIRST_FREE;
ins_did <= INSERT_DID_TYPE2;
ins_sdid <= INSERT_SDID4;
ins_dc <= INSERT_DC;
when others =>
replace <= '0';
ins_start <= (others => '0');
ins_did <= (others => '0');
ins_sdid <= (others => '0');
ins_dc <= (others => '0');
end case;
end process;
--
-- This code replaces the data from the memory with inserted ANC packet data.
--
process(clk)
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