📄 test_anc_demux.vhd
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-- test_anc_demux.vhd
--
-- Testbench for ANC packet DEMUX function of the anc_edh_processor module
--
--
--
-- Author: John F. Snow
-- Staff Applications Engineer
--
-- Video Applications
-- Advanced Products Group
-- Xilinx, Inc.
--
-- Copyright (c) 2002 Xilinx, Inc.
-- All rights reserved
--
-- Date: May. 8, 2002
--
-- RESTRICTED RIGHTS LEGEND
--
-- This software has not been published by the author, and
-- has been disclosed to others for the purpose of enhancing
-- and promoting design productivity in Xilinx products.
--
-- Therefore use, duplication or disclosure, now and in the
-- future should give consideration to the productivity
-- enhancements afforded the user of this code by the author's
-- efforts. Thank you for using our products !
--
-- Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY
-- WHATSOEVER AND XILINX SPECIFICALLY DISCLAIMS ANY
-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
-- A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
--
-- Revision:
-- May. 8, 2002 Release
--
--
--------------------------------------------------------------------------------
-- !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
-- IMPORTANT NOTE:
--
-- This testbench uses shared variables and VHDL '93 file I/O syntax. It must
-- be compiled by a VHDL '93 compliant compiler. In ModelSim, the default is
-- to generated errors on VHDL '93 specific syntax and the -93 flag must be
-- used.
--!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
--
-- This testbench tests the ANC packet demuxing capabilities of the
-- anc_edh_processor module.
--
-- The testbench first waits for the video decoder module to lock to the video.
-- Then, it inserts ANC packets into the horizontal blanking interval on five
-- consecutive lines. On the first line, a Type 1 packet is inserted which
-- should match the DID code on the did_a input. On the remaining lines, Type 2
-- packets are inserted that should match the DID/SDID pairs on the a through d
-- inputs sequentially (line 2 matches the "a" pair, line 3 matches the "b"
-- pair, etc.)
--
-- On the last line, the one that matches the "d" input pair, the del_pkt input
-- is asserted to cause the packet to be marked for deletion in the video
-- stream.
--
library ieee;
use std.textio.all;
use ieee.std_logic_textio.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use work.anc_edh_pkg.all;
entity test_anc_demux is
constant MAX_MEM : integer := 900900; -- Size of memory needed to hold 1 frame NTSC
type mem_type is array (MAX_MEM - 1 downto 0) of video_type;
end;
architecture sim of test_anc_demux is
shared variable memory : mem_type; -- Memory array holding test video
--------------------------------------------------------------------------------
-- Constant definitions
--
constant FIRST_EDH : integer := 13977; -- Position in memory of start of 1st EDH packet
constant SECOND_EDH : integer := 465285; -- Position in memory of start of 2nd EDH packet
-- These constants specify the positions of some words in the ANC packet.
constant DID_WORD : integer := 3;
constant DBN_WORD : integer := 4;
constant DC_WORD : integer := 5;
-- These constants define the values of certain words in inserted ANC packets.
constant ADF0 : video_type := "0000000000";
constant ADF1 : video_type := "1111111111";
constant INSERT_DID_TYPE1 :ubyte_type := ubyte_type(TO_UNSIGNED(16#c5#, ubyte_type'length));
constant INSERT_DID_TYPE2 :ubyte_type := ubyte_type(TO_UNSIGNED(16#7f#, ubyte_type'length));
constant INSERT_DBN : ubyte_type := ubyte_type(TO_UNSIGNED(16#00#, ubyte_type'length));
constant INSERT_SDID1 : ubyte_type := ubyte_type(TO_UNSIGNED(16#10#, ubyte_type'length));
constant INSERT_SDID2 : ubyte_type := ubyte_type(TO_UNSIGNED(16#20#, ubyte_type'length));
constant INSERT_SDID3 : ubyte_type := ubyte_type(TO_UNSIGNED(16#30#, ubyte_type'length));
constant INSERT_SDID4 : ubyte_type := ubyte_type(TO_UNSIGNED(16#40#, ubyte_type'length));
constant INSERT_DC : ubyte_type := ubyte_type(TO_UNSIGNED(16#08#, ubyte_type'length));
constant START_LINE : vpos_type := "0100101100"; -- 300
constant START_LINE_PLUS_1 : vpos_type := "0100101101"; -- 301
constant START_LINE_PLUS_2 : vpos_type := "0100101110"; -- 302
constant START_LINE_PLUS_3 : vpos_type := "0100101111"; -- 303
constant START_LINE_PLUS_4 : vpos_type := "0100110000"; -- 304
constant FIRST_FREE : hpos_type := hpos_type(TO_UNSIGNED(1477,hpos_type'length));
--
-- This constant specifies the number of cycles of clock latency through the
-- anc_edh_processor, including video decoder latency.
--
constant LATENCY : integer := 10;
--------------------------------------------------------------------------------
-- Signal definitions
--
--
-- These signals connect to the modules in the test bench
--
signal clk : std_ulogic := '0'; -- clock signal
signal enclk : std_ulogic := '1'; -- clock enable
signal rst : std_ulogic := '1'; -- reset signal
signal d: video_type; -- output of memory array
signal vid_in : video_type; -- video input to module
signal std_locked : std_ulogic; -- video standard dectector locked
signal std : vidstd_type; -- video standard code
signal trs : std_ulogic; -- video decoder TRS
signal vid_out : video_type; -- video output of edh_processor
signal f : std_ulogic; -- field indicator
signal v : std_ulogic; -- vertical blanking indicator
signal h : std_ulogic; -- horizontal blanking indicator
signal hcnt : hpos_type; -- horizontal counter
signal vcnt : vpos_type; -- vertical counter
signal sync_switch: std_ulogic; -- sync switching line
signal locked: std_ulogic; -- flywheel locked
signal eav_next: std_ulogic; -- EAV is next
signal sav_next: std_ulogic; -- SAV is next
signal xyz_word: std_ulogic; -- current word is XYZ word
signal anc_next: std_ulogic; -- ANC is next
signal edh_next: std_ulogic; -- EDH is next
signal rx_ce: std_ulogic; -- clock enable
signal edh_packet: std_ulogic; -- edh processor EDH packet indicator
signal edh_missing: std_ulogic; -- edh packet was missing
signal edh_parity_err: std_ulogic; -- edh packet parity error
signal edh_chksum_err: std_ulogic; -- edh packet checksum error
signal edh_format_err: std_ulogic; -- edh packet format error
signal rx_ap_flags: edh_flgset_type; -- received edh packet AP flags
signal rx_ff_flags: edh_flgset_type; -- received edh packet FF flags
signal rx_anc_flags: edh_flgset_type; -- recevied edh packet ANC flags
signal ap_flags: edh_flgset_type; -- transmitted edh packet AP flags
signal ff_flags: edh_flgset_type; -- transmitted edh packet FF flags
signal anc_flags: edh_flgset_type; -- transmitted edh packet ANC flags
signal errcnt: edh_errcnt_type; -- count of fields containing EDH errors
signal anc_idh_local: std_ulogic := '0'; -- controls the ANC IDH local input to EDH proc
signal anc_ues_local: std_ulogic := '0'; -- controls the ANC UES local input to EDH proc
signal ap_idh_local: std_ulogic := '0'; -- controls the AP IDH local input to EDH proc
signal ff_idh_local: std_ulogic := '0'; -- controls the FF IDH local input to EDH proc
signal errcnt_flg_en: edh_allflg_type -- controls the error count flag enables
:= "1111111111111111";
signal did_a : ubyte_type; -- "A" set DID match input
signal sdid_a : ubyte_type; -- "A" set SDID match input
signal en_a : std_ulogic; -- "A" set SDID match input
signal del_pkt_a : std_ulogic; -- "A" set delete packet input
signal did_b : ubyte_type; -- "B" set DID match input
signal sdid_b : ubyte_type; -- "B" set SDID match input
signal en_b : std_ulogic; -- "B" set SDID match input
signal del_pkt_b : std_ulogic; -- "B" set delete packet input
signal did_c : ubyte_type; -- "C" set DID match input
signal sdid_c : ubyte_type; -- "C" set SDID match input
signal en_c : std_ulogic; -- "C" set SDID match input
signal del_pkt_c : std_ulogic; -- "C" set delete packet input
signal did_d : ubyte_type; -- "D" set DID match input
signal sdid_d : ubyte_type; -- "D" set SDID match input
signal en_d : std_ulogic; -- "D" set SDID match input
signal del_pkt_d : std_ulogic; -- "D" set delete packet input
signal anc_out : video_type; -- demuxed ANC packet data output
signal anc_out_valid : std_ulogic; -- ANC packet data out is valid
signal anc_match: -- indicates which DID/SDID set matches packet
std_ulogic_vector(1 downto 0);
signal did : std_ulogic; -- DID word on anc_out
signal dbn : std_ulogic; -- DBN word on anc_out
signal sdid : std_ulogic; -- SDID word on anc_out
signal dc : std_ulogic; -- DC word on anc_out
signal udw : std_ulogic; -- UDW word on anc_out
signal cs : std_ulogic; -- CS word on anc_out
signal packet_flags : edh_pktflg_type; -- vector containing the packet error flags listed below
--
-- These signals control the testbench
--
type dly_video_type is array (LATENCY-1 downto 0) of video_type;
signal i: integer; -- index into memory array
signal frames: integer; -- counts number of frames during test
signal error_found: boolean := false; -- asserted when a simulation error is detected
signal expected_vid: video_type; -- expected video value
signal match_code : -- used to generated expected data
std_ulogic_vector(1 downto 0);
signal type_code : integer; -- packet type code
signal expected_anc : video_type; -- expected anc data out
signal expected_match : -- expected DID/SDID match set code
std_ulogic_vector(1 downto 0);
signal expected_valid : std_ulogic; -- expected anc_out_valid value
signal expected_did : std_ulogic; -- expected DID signal
signal expected_dbn : std_ulogic; -- expected DBN signal
signal expected_sdid : std_ulogic; -- expected SDID signal
signal expected_dc : std_ulogic; -- expected DC signal
signal expected_udw : std_ulogic; -- expected UDW signal
signal expected_cs : std_ulogic; -- expected CS signal
signal dly_vid : dly_video_type; -- delays vid_in for output comparison
signal replace : std_ulogic := '0'; -- replaced memory output with ANC packet data when asserted
signal ins_start : -- insert starting position for ANC packet
hpos_type := (others => '0');
signal ins_did : -- inserted DID value
ubyte_type := (others => '0');
signal ins_sdid : -- inserted SDID/DBN value
ubyte_type := (others => '0');
signal ins_dc : -- inserted DC value
ubyte_type := (others => '0');
signal checksum : -- inserted checksum value
cksum_type := (others => '0');
signal VCC : std_ulogic := '1';
signal GND : std_ulogic := '0';
signal GND8 : udwadr_type := "00000000";
signal GND10 : video_type := "0000000000";
component anc_edh_processor
port (
clk: in std_ulogic; -- clock input
ce: in std_ulogic; -- clock enable
rst: in std_ulogic; -- async reset input
-- video decoder inputs
vid_in: in video_type; -- input video
reacquire: in std_ulogic; -- forces autodetect to reacquire the video standard
en_sync_switch: in std_ulogic; -- enables synchronous switching
en_trs_blank: in std_ulogic; -- enables TRS blanking when asserted
-- EDH flag inputs
anc_idh_local: in std_ulogic; -- ANC IDH flag input
anc_ues_local: in std_ulogic; -- ANC UES flag input
ap_idh_local: in std_ulogic; -- AP IDH flag input
ff_idh_local: in std_ulogic; -- FF IDH flag input
errcnt_flg_en: in edh_allflg_type;-- selects which error flags increment the error counter
clr_errcnt: in std_ulogic; -- clears the error counter
receive_mode: in std_ulogic; -- 1 enables receiver, 0 for generate only
-- ANC demux inputs
en_a: in std_ulogic; -- enable for DID A decoder
did_a: in ubyte_type; -- first DID code to match
sdid_a: in ubyte_type; -- first SDID code to match
del_pkt_a: in std_ulogic; -- packet will be deleted if asserted
en_b: in std_ulogic; -- enable for DID B decoder
did_b: in ubyte_type; -- second DID code to match
sdid_b: in ubyte_type; -- second SDID code to match
del_pkt_b: in std_ulogic; -- packet will be deleted if asserted
en_c: in std_ulogic; -- enable for DID C decoder
did_c: in ubyte_type; -- third DID code to match
sdid_c: in ubyte_type; -- third SDID code to match
del_pkt_c: in std_ulogic; -- packet will be deleted if asserted
en_d: in std_ulogic; -- enable for DID D decoder
did_d: in ubyte_type; -- fourth DID code to match
sdid_d: in ubyte_type; -- fourth SDID code to match
del_pkt_d: in std_ulogic; -- packet will be deleted if asserted
-- ANC mux inputs
hanc_pkt: in std_ulogic; -- ANC packet to be sent can be inserted into HANC space
vanc_pkt: in std_ulogic; -- ANC packet to be sent can be inserted into VANC space
pkt_rdy_in: in std_ulogic; -- indicates packet has been loaded into input regs
calc_udw_parity:in std_ulogic; -- indicates that module should calculate parity on UDW
anc_in: in video_type; -- input data bus
ld_did: in std_ulogic; -- load DID register
ld_dbn: in std_ulogic; -- load SDID/DBN register
ld_dc: in std_ulogic; -- load DC register
ld_udw: in std_ulogic; -- loads the UDW RAM
udw_wr_adr: in udwadr_type; -- UDW RAM write address
-- video and decoded video timing outputs
vid_out: out video_type; -- output video stream with EDH packets inserted
std: out vidstd_type; -- video standard code
std_locked: out std_ulogic; -- video standard detector is locked
trs: out std_ulogic; -- asserted during flywheel generated TRS symbol
field: out std_ulogic; -- field indicator
v_blank: out std_ulogic; -- vertical blanking indicator
h_blank: out std_ulogic; -- horizontal blanking indicator
horz_count: out hpos_type; -- horizontal position
vert_count: out vpos_type; -- vertical position
sync_switch: out std_ulogic; -- asserted on lines where synchronous switching is allowed
locked: out std_ulogic; -- asserted when flywheel is synchronized to video
eav_next: out std_ulogic; -- next word is first word of EAV
sav_next: out std_ulogic; -- next word is first word of SAV
xyz_word: out std_ulogic; -- current word is the XYZ word of a TRS
anc_next: out std_ulogic; -- next word is first word of a received ANC packet
edh_next: out std_ulogic; -- next word is first word of a received EDH packet
-- EDH flag outputs
rx_ap_flags: out edh_flgset_type;-- AP error flags received from last EDH packet
rx_ff_flags: out edh_flgset_type;-- FF error flags received from last EDH packet
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