test_ae_edh.vhd

XAPP299 version 1.0 reference design files

        
            if (edh_parity_err = '0' and expected_parity_err = '1') then
                write(l, expected_parity_err_str);
                writeline(output, l);
                error_found <= true;
            end if;

            if (edh_format_err = '1' and expected_format_err = '0') then
                write(l, unexpected_pkt_format_err_str);
                writeline(output, l);
                error_found <= true;
            end if;

            if (edh_format_err = '0' and expected_format_err = '1') then
                write(l, expected_pkt_format_err_str);
                writeline(output, l);
                error_found <= true;
            end if;
        end if; 
    end process;        


    --
    -- Delay registers that delay the video and video timing outputs of the video
    -- decoder so they can be compared with the outputs of the edh_processor.
    --
    process(clk)
    begin
        if (clk'event and clk = '1') then
            for j in 0 to LATENCY-2 loop
                dly_std(j+1) <= dly_std(j);
                dly_std_locked(j+1) <= dly_std_locked(j);
                dly_vid(j+1) <= dly_vid(j);
                dly_f(j+1) <= dly_f(j);
                dly_v(j+1) <= dly_v(j);
                dly_h(j+1) <= dly_h(j);
                dly_hcnt(j+1) <= dly_hcnt(j);
                dly_vcnt(j+1) <= dly_vcnt(j);
                dly_sync_switch(j+1) <= dly_sync_switch(j);
                dly_eav_next(j+1) <= dly_eav_next(j);
                dly_sav_next(j+1) <= dly_sav_next(j);
                dly_xyz_word(j+1) <= dly_xyz_word(j);
                dly_anc_next(j+1) <= dly_anc_next(j);
                dly_edh_next(j+1) <= dly_edh_next(j);
            end loop;

            dly_std(0) <= ep_dec_std;
            dly_std_locked(0) <= ep_dec_std_locked;
            dly_vid(0) <= ep_dec_vid;
            dly_f(0) <= ep_dec_f;
            dly_v(0) <= ep_dec_v;
            dly_h(0) <= ep_dec_h;
            dly_hcnt(0) <= ep_dec_hcnt;
            dly_vcnt(0) <= ep_dec_vcnt;
            dly_sync_switch(0) <= ep_dec_sync_switch;
            dly_eav_next(0) <= ep_dec_eav_next;
            dly_sav_next(0) <= ep_dec_sav_next;
            dly_xyz_word(0) <= ep_dec_xyz_word;
            dly_anc_next(0) <= ep_dec_anc_next;
            dly_edh_next(0) <= ep_dec_edh_next; 
        end if;
    end process;


    --
    -- This code checks that the output video timing signals match the video
    -- decoders output signals (delayed by the delay registers above.
    --
    process(clk)
        variable dly_std_err_str :      string(1 to 47) 
                                        := "std output doesn't match video decoder's output";
        variable dly_std_locked_err_str : string(1 to 54) 
                                        := "std_locked output doesn't match video decoder's output";
        variable dly_f_err_str :        string(1 to 54) 
                                        := "std_locked output doesn't match video decoder's output";
    begin
        if (clk'event and clk = '0') then
                
            if (locked = '1') then
                assert (std = dly_std(LATENCY-1))
                    report "std output doesn't match video decoder's output"
                    severity error;
                     
                assert (std_locked = dly_std_locked(LATENCY-1))
                    report "std_locked output doesn't match video decoder's output"
                    severity error;

                assert (f = dly_f(LATENCY-1))
                    report "f output doesn't match video decoder's output"
                    severity error;
                    
                assert (v = dly_v(LATENCY-1))
                    report "v output doesn't match video decoder's output"
                    severity error;
                    
                assert (h = dly_h(LATENCY-1))
                    report "h output doesn't match video decoder's output"
                    severity error;
                    
                assert (hcnt = dly_hcnt(LATENCY-1))
                    report "hcnt output doesn't match video decoder's output"
                    severity error;
                    
                assert (vcnt = dly_vcnt(LATENCY-1))
                    report "vcnt output doesn't match video decoder's output"
                    severity error;
                    
                assert (sync_switch = dly_sync_switch(LATENCY-1))
                    report "sync_switch output doesn't match video decoder's output"
                    severity error;
                    
                assert (eav_next = dly_eav_next(LATENCY-1))
                    report "eav_next output doesn't match video decoder's output"
                    severity error;
                    
                assert (sav_next = dly_sav_next(LATENCY-1))
                    report "sav_next output doesn't match video decoder's output"
                    severity error;
                    
                assert (xyz_word = dly_xyz_word(LATENCY-1))
                    report "xyz_word output doesn't match video decoder's output"
                    severity error;
                    
                assert (anc_next = dly_anc_next(LATENCY-1))
                    report "anc_next output doesn't match video decoder's output"
                    severity error;

                assert (edh_next = dly_edh_next(LATENCY-1))
                    report "edh_next output doesn't match video decoder's output"
                    severity error;
            end if;
        end if;
    end process;    

    --
    -- This clode checks that the vid_out signal matches the video out of the video
    -- decoder during the active portions of the video display. The edh_processor
    -- should never modify the active portion of the video.
    --  
    process(clk)
    begin
        if (clk'event and clk = '0') then
            if (locked = '1' and h = '0' and v = '0') then
                assert (vid_out = dly_vid(LATENCY-1))
                    report "vid_out output doesn't match video decoder's output"
                    severity error;
            end if; 
        end if;
    end process;

    --
    -- The code below verifies the formatting of the EDH packets generated by the
    -- edh_processor. Other code in this testbench verifies that the CRC values and
    -- flags are as expected. This code verifies that the CRC values and flags were
    -- formatted into an EDH packet properly and that the checksum for the EDH
    -- packet is valid.
    --
    process(clk)
    variable edh_word :     integer;
    variable edh_data :     std_ulogic_vector(7 downto 0);
    variable edh_parity :   std_ulogic;
    variable edh_expected : std_ulogic_vector(9 downto 0);
    variable edh_checksum : std_ulogic_vector(8 downto 0);

    begin
        if (clk'event and clk = '0') then
            
            if (locked = '1' and edh_next = '1') then
                edh_word := 0;
            end if;

            if (locked = '1' and edh_packet = '1') then
                case edh_word is
                    when 0 =>
                        assert (vid_out = "0000000000")
                            report "vid_out isn't equal to first word of ADF (000)"
                            severity error;
                                
                    when 1 =>
                        assert (vid_out = "1111111111")
                            report "vid_out isn't equal to second word of ADF (3FF)"
                            severity error;
                                                        
                    when 2 =>   
                        assert (vid_out = "1111111111")
                            report "vid_out isn't equal to third word of ADF (3FF)"
                            severity error;
                                                        
                    when 3 =>
                        assert (vid_out = "0111110100")
                            report "vid_out isn't equal to DID word of EDH (1F4)"
                            severity error;

                        edh_checksum := vid_out(8 downto 0);

                    when 4 =>
                        assert (vid_out = "1000000000")
                            report "vid_out isn't equal to DBN word of EDH (200)"
                            severity error;

                        edh_checksum := std_ulogic_vector(std_logic_vector(edh_checksum) 
                                        + std_logic_vector(vid_out(8 downto 0)));

                    when 5 =>
                        assert (vid_out = "0100010000")
                            report "vid_out isn't equal to DC word of EDH (110)"
                            severity error;

                        edh_checksum := std_ulogic_vector(std_logic_vector(edh_checksum)
                                         + std_logic_vector(vid_out(8 downto 0)));

                    when 6 =>
                        edh_data := (ep_ap_crc(5 downto 0) & "00");
                        edh_parity := calc_parity(edh_data);
                        edh_expected := (not edh_parity & edh_parity & edh_data);
                        edh_checksum := std_ulogic_vector(std_logic_vector(edh_checksum) 
                                        + std_logic_vector(edh_expected(8 downto 0)));

                        assert (vid_out = edh_expected)
                            report "vid_out doesn't match first AP CRC word of EDH packet"
                            severity error;

                    when 7 =>
                        edh_data := (ep_ap_crc(11 downto 6) & "00");
                        edh_parity := calc_parity(edh_data);
                        edh_expected := (not edh_parity & edh_parity & edh_data);
                        edh_checksum := std_ulogic_vector(std_logic_vector(edh_checksum) 
                                        + std_logic_vector(edh_expected(8 downto 0)));

                        assert (vid_out = edh_expected)
                            report "vid_out doesn't match second AP CRC word of EDH packet"
                            severity error;

                    when 8 =>
                        edh_data := (ep_ap_crc_valid & '0' & ep_ap_crc(15 downto 12) & "00");
                        edh_parity := calc_parity(edh_data);
                        edh_expected := (not edh_parity & edh_parity & edh_data);
                        edh_checksum := std_ulogic_vector(std_logic_vector(edh_checksum) 
                                        + std_logic_vector(edh_expected(8 downto 0)));

                        assert (vid_out = edh_expected)
                            report "vid_out doesn't match third AP CRC word of EDH packet"
                            severity error;

                    when 9 =>
                        edh_data := (ep_ff_crc(5 downto 0) & "00");
                        edh_parity := calc_parity(edh_data);
                        edh_expected := (not edh_parity & edh_parity & edh_data);
                        edh_checksum := std_ulogic_vector(std_logic_vector(edh_checksum) 
                                        + std_logic_vector(edh_expected(8 downto 0)));

                        assert (vid_out = edh_expected)
                            report "vid_out doesn't match first FF CRC word of EDH packet"
                            severity error;

                    when 10 =>
                        edh_data := (ep_ff_crc(11 downto 6) & "00");
                        edh_parity := calc_parity(edh_data);
                        edh_expected := (not edh_parity & edh_parity & edh_data);
                        edh_checksum := std_ulogic_vector(std_logic_vector(edh_checksum) 
                                        + std_logic_vector(edh_expected(8 downto 0)));
                        
                        assert (vid_out = edh_expected)
                            report "vid_out doesn't match second FF CRC word of EDH packet"
                            severity error;

                    when 11 =>
                        edh_data := (ep_ff_crc_valid & '0' & ep_ff_crc(15 downto 12) & "00");
                        edh_parity := calc_parity(edh_data);
                        edh_expected := (not edh_parity & edh_parity & edh_data);
                        edh_checksum := std_ulogic_vector(std_logic_vector(edh_checksum) 
                                        + std_logic_vector(edh_expected(8 downto 0)));
                        
                        assert (vid_out = edh_expected)
                            report "vid_out doesn't match third FF CRC word of EDH packet"
                            severity error;

                    when 12 =>
                        edh_data := ('0' & ep_anc_flags & "00");
                        edh_parity := calc_parity(edh_data);
                        edh_expected := (not edh_parity & edh_parity & edh_data);
                        edh_checksum := std_ulogic_vector(std_logic_vector(edh_checksum)