📄 test_ae_edh.vhd
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signal ep_dec_vcnt: vpos_type;
signal ep_dec_sync_switch: std_ulogic;
signal ep_dec_locked: std_ulogic;
signal ep_dec_eav_next: std_ulogic;
signal ep_dec_sav_next: std_ulogic;
signal ep_dec_xyz_word: std_ulogic;
signal ep_dec_anc_next: std_ulogic;
signal ep_dec_edh_next: std_ulogic;
signal ep_ap_crc: crc16_type;
signal ep_ap_crc_valid: std_ulogic;
signal ep_ff_crc: crc16_type;
signal ep_ff_crc_valid: std_ulogic;
signal ep_anc_flags: edh_flgset_type;
signal ep_ap_flags: edh_flgset_type;
signal ep_ff_flags: edh_flgset_type;
--
-- These signals are used to strap module inputs high or low.
--
signal VCC : std_ulogic := '1';
signal GND : std_ulogic := '0';
signal GND8 : std_ulogic_vector(7 downto 0) := "00000000";
signal GND10 : std_ulogic_vector(9 downto 0) := "0000000000";
component anc_edh_processor
port (
clk: in std_ulogic; -- clock input
ce: in std_ulogic; -- clock enable
rst: in std_ulogic; -- async reset input
-- video decoder inputs
vid_in: in video_type; -- input video
reacquire: in std_ulogic; -- forces autodetect to reacquire the video standard
en_sync_switch: in std_ulogic; -- enables synchronous switching
en_trs_blank: in std_ulogic; -- enables TRS blanking when asserted
-- EDH flag inputs
anc_idh_local: in std_ulogic; -- ANC IDH flag input
anc_ues_local: in std_ulogic; -- ANC UES flag input
ap_idh_local: in std_ulogic; -- AP IDH flag input
ff_idh_local: in std_ulogic; -- FF IDH flag input
errcnt_flg_en: in edh_allflg_type;-- selects which error flags increment the error counter
clr_errcnt: in std_ulogic; -- clears the error counter
receive_mode: in std_ulogic; -- 1 enables receiver, 0 for generate only
-- ANC demux inputs
en_a: in std_ulogic; -- enable for DID A decoder
did_a: in ubyte_type; -- first DID code to match
sdid_a: in ubyte_type; -- first SDID code to match
del_pkt_a: in std_ulogic; -- packet will be deleted if asserted
en_b: in std_ulogic; -- enable for DID B decoder
did_b: in ubyte_type; -- second DID code to match
sdid_b: in ubyte_type; -- second SDID code to match
del_pkt_b: in std_ulogic; -- packet will be deleted if asserted
en_c: in std_ulogic; -- enable for DID C decoder
did_c: in ubyte_type; -- third DID code to match
sdid_c: in ubyte_type; -- third SDID code to match
del_pkt_c: in std_ulogic; -- packet will be deleted if asserted
en_d: in std_ulogic; -- enable for DID D decoder
did_d: in ubyte_type; -- fourth DID code to match
sdid_d: in ubyte_type; -- fourth SDID code to match
del_pkt_d: in std_ulogic; -- packet will be deleted if asserted
-- ANC mux inputs
hanc_pkt: in std_ulogic; -- ANC packet to be sent can be inserted into HANC space
vanc_pkt: in std_ulogic; -- ANC packet to be sent can be inserted into VANC space
pkt_rdy_in: in std_ulogic; -- indicates packet has been loaded into input regs
calc_udw_parity:in std_ulogic; -- indicates that module should calculate parity on UDW
anc_in: in video_type; -- input data bus
ld_did: in std_ulogic; -- load DID register
ld_dbn: in std_ulogic; -- load SDID/DBN register
ld_dc: in std_ulogic; -- load DC register
ld_udw: in std_ulogic; -- loads the UDW RAM
udw_wr_adr: in udwadr_type; -- UDW RAM write address
-- video and decoded video timing outputs
vid_out: out video_type; -- output video stream with EDH packets inserted
std: out vidstd_type; -- video standard code
std_locked: out std_ulogic; -- video standard detector is locked
trs: out std_ulogic; -- asserted during flywheel generated TRS symbol
field: out std_ulogic; -- field indicator
v_blank: out std_ulogic; -- vertical blanking indicator
h_blank: out std_ulogic; -- horizontal blanking indicator
horz_count: out hpos_type; -- horizontal position
vert_count: out vpos_type; -- vertical position
sync_switch: out std_ulogic; -- asserted on lines where synchronous switching is allowed
locked: out std_ulogic; -- asserted when flywheel is synchronized to video
eav_next: out std_ulogic; -- next word is first word of EAV
sav_next: out std_ulogic; -- next word is first word of SAV
xyz_word: out std_ulogic; -- current word is the XYZ word of a TRS
anc_next: out std_ulogic; -- next word is first word of a received ANC packet
edh_next: out std_ulogic; -- next word is first word of a received EDH packet
-- EDH flag outputs
rx_ap_flags: out edh_flgset_type;-- AP error flags received from last EDH packet
rx_ff_flags: out edh_flgset_type;-- FF error flags received from last EDH packet
rx_anc_flags: out edh_flgset_type;-- ANC error flags freceived from last EDH packet
ap_flags: out edh_flgset_type;-- transmitted AP error flags from last field
ff_flags: out edh_flgset_type;-- transmitted FF error flags from last field
anc_flags: out edh_flgset_type;-- transmitted ANC error flags from last field
packet_flags: out edh_pktflg_type;-- error flags related to the received packet processing
errcnt: out edh_errcnt_type;-- errored fields counter
edh_packet: out std_ulogic; -- asserted during all words of a generated EDH packet
-- ANC demux outputs
anc_out: out video_type; -- output packet data
anc_out_valid: out std_ulogic; -- asserted while all words of a matching packet are on anc_out
anc_match: out -- indicates DID/SDID combination matched the current packet
std_ulogic_vector(1 downto 0);
did: out std_ulogic; -- asserted when a DID word from a matching packet is on anc_out
dbn: out std_ulogic; -- asserted when a DBN word from a matching packet is on anc_out
sdid: out std_ulogic; -- asserted when an SDID word from a matching packet is on anc_out
dc: out std_ulogic; -- asserted when a DC word from a matching packet is on anc_out
udw: out std_ulogic; -- asserted when a UDW word from a matching packet is on anc_out
cs: out std_ulogic; -- asserted when a CS word from a matching packet is on anc_out
-- ANC mux outputs
pkt_in_empty: out std_ulogic); -- module is ready for input packet to be loaded
end component;
--
-- Checksum function
--
function calc_parity(d : std_ulogic_vector(7 downto 0)) return std_ulogic is
begin
return (d(7) xor d(6) xor d(5) xor d(4) xor d(3) xor d(2) xor d(1) xor d(0));
end calc_parity;
begin
--
-- Run init_signal_spy to map the some of the signals internal to the
-- anc_edh_processor module to testbench signals so they can be monitored.
--
process
begin
init_signal_spy("/U1/dec_std", "/ep_dec_std", 0);
init_signal_spy("/U1/dec_std_locked", "/ep_dec_std_locked", 0);
init_signal_spy("/U1/dec_vid", "/ep_dec_vid", 0);
init_signal_spy("/U1/dec_f", "/ep_dec_f", 0);
init_signal_spy("/U1/dec_v", "/ep_dec_v", 0);
init_signal_spy("/U1/dec_h", "/ep_dec_h", 0);
init_signal_spy("/U1/dec_hcnt", "/ep_dec_hcnt", 0);
init_signal_spy("/U1/dec_vcnt", "/ep_dec_vcnt", 0);
init_signal_spy("/U1/dec_sync_switch", "/ep_dec_sync_switch", 0);
init_signal_spy("/U1/dec_locked", "/ep_dec_locked", 0);
init_signal_spy("/U1/dec_eav_next", "/ep_dec_eav_next", 0);
init_signal_spy("/U1/dec_sav_next", "/ep_dec_sav_next", 0);
init_signal_spy("/U1/dec_xyz_word", "/ep_dec_xyz_word", 0);
init_signal_spy("/U1/dec_anc_next", "/ep_dec_anc_next", 0);
init_signal_spy("/U1/dec_edh_next", "/ep_dec_edh_next", 0);
init_signal_spy("/U1/ap_crc", "/ep_ap_crc", 0);
init_signal_spy("/U1/ap_crc_valid", "/ep_ap_crc_valid", 0);
init_signal_spy("/U1/ff_crc", "/ep_ff_crc", 0);
init_signal_spy("/U1/ff_crc_valid", "/ep_ff_crc_valid", 0);
init_signal_spy("/U1/anc_flags", "/ep_anc_flags", 0);
init_signal_spy("/U1/ap_flags", "/ep_ap_flags", 0);
init_signal_spy("/U1/ff_flags", "/ep_ff_flags", 0);
wait;
end process;
--
-- Instantiate the ANC/EDH processor module
--
U1 : anc_edh_processor
port map (
clk => clk,
ce => rx_ce,
rst => rst,
vid_in => vid_in,
reacquire => GND,
en_sync_switch => VCC,
en_trs_blank => VCC,
anc_idh_local => anc_idh_local,
anc_ues_local => anc_ues_local,
ap_idh_local => ap_idh_local,
ff_idh_local => ff_idh_local,
errcnt_flg_en => errcnt_flg_en,
clr_errcnt => GND,
receive_mode => VCC,
en_a => GND,
did_a => GND8,
sdid_a => GND8,
del_pkt_a => GND,
en_b => GND,
did_b => GND8,
sdid_b => GND8,
del_pkt_b => GND,
en_c => GND,
did_c => GND8,
sdid_c => GND8,
del_pkt_c => GND,
en_d => GND,
did_d => GND8,
sdid_d => GND8,
del_pkt_d => GND,
hanc_pkt => GND,
vanc_pkt => GND,
pkt_rdy_in => GND,
calc_udw_parity => GND,
anc_in => GND10,
ld_did => GND,
ld_dbn => GND,
ld_dc => GND,
ld_udw => GND,
udw_wr_adr => udw_wr_adr,
vid_out => vid_out,
std => std,
std_locked => std_locked,
trs => trs,
field => f,
v_blank => v,
h_blank => h,
horz_count => hcnt,
vert_count => vcnt,
sync_switch => sync_switch,
locked => locked,
eav_next => eav_next,
sav_next => sav_next,
xyz_word => xyz_word,
anc_next => anc_next,
edh_next => edh_next,
rx_ap_flags => rx_ap_flags,
rx_ff_flags => rx_ff_flags,
rx_anc_flags => rx_anc_flags,
ap_flags => ap_flags,
ff_flags => ff_flags,
anc_flags => anc_flags,
packet_flags => packet_flags,
errcnt => errcnt,
edh_packet => edh_packet,
anc_out => open,
anc_out_valid => open,
anc_match => open,
did => open,
dbn => open,
sdid => open,
dc => open,
udw => open,
cs => open,
pkt_in_empty => open);
edh_format_err <= packet_flags(3);
edh_chksum_err <= packet_flags(2);
edh_parity_err <= packet_flags(1);
edh_missing <= packet_flags(0);
--
-- Read in one frame of NTSC video into memory array
--
process
file infile: TEXT open read_mode is "C:/work/XAPP299/sim/one_frame.txt";
variable buf: line;
variable data: std_logic_vector(11 downto 0);
variable words: integer := 0;
variable good: boolean;
begin
while not (endfile(infile)) loop
readline(infile, buf); -- read a line from file into buffer
for i in 0 to 15 loop -- there are 16 words per line in the file
exit when words = MAX_MEM; -- last line doesn't contain 16 words so put an early escape mechanism here
hread(buf, data, good); -- read one word from the buffer
assert good -- make sure the read was OK
report "Text I/O read error"
severity failure;
memory(words) := video_type(data(9 downto 0)); -- write word to the memory array
words := words + 1;
end loop;
end loop;
wait;
end process;
--
-- Generate a clock signal at 27 MHz.
--
clk <= enclk and not clk after 18.5 ns;
rx_ce <= '1';
--
-- Assert the reset signal for the first few clock cycles
--
process
begin
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