test_ae_edh.vhd

XAPP299 version 1.0 reference design files

--------------------------------------------------------------------------------
-- test_ae_edh.vhd
--
-- Tests the EDH processing capabilities of the anc_edh_processor module
--
--
--
--                  Author: John F. Snow
--                  Staff Applications Engineer
--
--                  Video Applications
--                  Advanced Products Group
--                  Xilinx, Inc.
--
--                  Copyright (c) 2002 Xilinx, Inc.
--                  All rights reserved
--
--                  Date:   May 8, 2002
--
--                  RESTRICTED RIGHTS LEGEND
--
--      This software has not been published by the author, and 
--      has been disclosed to others for the purpose of enhancing 
--      and promoting design productivity in Xilinx products.
--
--      Therefore use, duplication or disclosure, now and in the 
--      future should give consideration to the productivity 
--      enhancements afforded the user of this code by the author's 
--      efforts.  Thank you for using our products !
--
-- Disclaimer:  THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY 
--              WHATSOEVER AND XILINX SPECIFICALLY DISCLAIMS ANY 
--              IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
--              A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
--
-- Revision:
--              May 8, 2002     Release
--              
--------------------------------------------------------------------------------
--
-- !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
-- IMPORTANT NOTE:
--
-- This testbench uses shared variables and VHDL '93 file I/O syntax. It must
-- be compiled by a VHDL '93 compliant compiler. In ModelSim, the default is
-- to generated errors on VHDL '93 specific syntax and the -93 flag must be
-- used.
--
-- This testbench also uses the ModelSim function init_signal_spy to monitor
-- some signals down in the hierarchy.
-- !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
--
-- This testbench is functional equivalent test_edh but runs on the
-- anc_edh_processor module. The testbench runs for eight frames. A data file 
-- called one_frame.txt is loaded into a memory array and used as the source 
-- data into the edh_processor every frame. This data file contains a video test
-- pattern, along with embedded EDH and ANC packets. The testbench sometimes 
-- substitutes values in place of the values from the data file in order to 
-- force certain error conditions to determine if the edh_processor detects 
-- them.
-- 
-- Field 0: The video decoder is synchronizing during this field. All errors are
-- ignored.
-- 
-- Field 1; No errors are expected during this field. The data from data file is
-- not modified. Any errors occurring in this field would indicate an error with
-- the design.
-- 
-- Field 2: The test bench forces an ANC IDH condition in this field to make 
-- sure it gets encoded into the outgoing EDH packet.
-- 
-- Field 3: The test bench forces an ANC UES condition in this field to make 
-- sure it gets encoded into the outgoing EDH packet.
-- 
-- Field 4: The test bench modifies the input EDH packet in two ways. It changes
-- the active-picture CRC value (the edh_processor should asserted the AP EDH
-- flag as a result). It also asserts the full-field EDH flag in the packet (the
-- edh_processor should clear the FF EDH bit and assert the FF EDA bit in the
-- outgoing EDH packet).
-- 
-- Field 5: The test bench forces a AP IDH error condition during this field. 
-- The AP IDH flag should be set in the outgoing packet.
-- 
-- Field 6: The test bench forces a FF IDH error condition during this field. 
-- The FF IDH flag should be set in the outgoing packet.
-- 
-- Field 7: The testbench forces the checksum of the EDH packet to an incorrect
-- value to make sure the edh_processor detects the error.
-- 
-- Field 8: The testbench removes the EDH packet from the input video stream and
-- checks that the edh_processor reports a missing EDH packet error. All the UES
-- flags in the outgoing packet will be asserted.
-- 
-- Field 9: The testbench forces the ANC IDH and UES error conditions to verify
-- that these flags get set in the outgoing EDH packet.
-- 
-- Field 10: The testbench forces the AP IDH and FF IDH error conditions to 
-- verify that these flags get set in the outgoing EDH packet.
-- 
-- Field 11: The value of the DBN word in the EDH packet is modified by the 
-- testbench. The edh_processor should detected a edh packet format error.  The 
-- UES flags of all three flag sets will be set in the outgoing EDH packet as a 
-- result.
-- 
-- Field 12: The testbench changes the value of one word in the inactive video.
-- This should cause the edh_processor to detect a FF CRC error. The corrupted 
-- word occurs in an ANC packet, so a checksum error for the ANC packet should 
-- also be detected.
-- 
-- Field 13: The testbench modifies the incoming EDH packet so that the AP EDH
-- flag is set. The outgoing EDH packet should have the AP EDH flag clear and 
-- the AP EDA flag set.
-- 
-- Field 14: No errors should be detected in this field.
-- 
-- Field 15: The testbench forces a parity error in the EDH packet. The 
-- edh_processor should detect and report this error.
-- 

library ieee;
use std.textio.all;
use ieee.std_logic_textio.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;

library modelsim_lib;
use modelsim_lib.util.all;      -- required for init_signal_spy

use work.anc_edh_pkg.all;

entity test_ae_edh is
    constant MAX_MEM : integer := 900900;   -- Size of memory needed to hold 1 frame NTSC
    type mem_type is 
            array (MAX_MEM - 1 downto 0) of video_type; 
end;

architecture sim of test_ae_edh is

shared variable memory :    mem_type;       -- Memory array holding test video

 
constant FIRST_EDH :    integer := 13977;   -- Position in memory of start of 1st EDH packet
constant SECOND_EDH :   integer := 465285;  -- Position in memory of start of 2nd EDH packet

-- These constants identify the various words in the EDH packet.
constant DID_WORD      : integer := 3;
constant DBN_WORD      : integer := 4;
constant DC_WORD       : integer := 5;
constant AP_CRC_WORD0  : integer := 6;
constant AP_CRC_WORD1  : integer := 7;
constant AP_CRC_WORD2  : integer := 8;
constant FF_CRC_WORD0  : integer := 9;
constant FF_CRC_WORD1  : integer := 10;
constant FF_CRC_WORD2  : integer := 11;
constant ANC_FLAG_WORD : integer := 12;
constant AP_FLAG_WORD  : integer := 13;
constant FF_FLAG_WORD  : integer := 14;
constant RSVD0         : integer := 15;
constant RSVD1         : integer := 16;
constant RSVD2         : integer := 17;
constant RSVD3         : integer := 18;
constant RSVD4         : integer := 19;
constant RSVD5         : integer := 20;
constant RSVD6         : integer := 21;
constant CS_WORD       : integer := 22;

 
--
-- These signals connect to the modules in the test bench
--
signal clk:             std_ulogic := '0';  -- clock signal
signal enclk :          std_ulogic := '1';  -- clock enable
signal rst:             std_ulogic := '1';  -- reset signal
signal d:               video_type;         -- output of memory array
signal vid_in:          video_type;         -- modified output of memory array
signal std_locked:      std_ulogic;         -- video standard dectector locked
signal std:             vidstd_type;        -- video standard code
signal trs:             std_ulogic;         -- video decoder TRS
signal vid_out:         video_type;         -- video output of edh_processor
signal f:               std_ulogic;         -- field indicator
signal v:               std_ulogic;         -- vertical blanking indicator
signal h:               std_ulogic;         -- horizontal blanking indicator
signal hcnt:            hpos_type;          -- horizontal counter
signal vcnt:            vpos_type;          -- vertical counter
signal sync_switch:     std_ulogic;         -- sync switching line
signal locked:          std_ulogic;         -- flywheel locked
signal eav_next:        std_ulogic;         -- EAV is next
signal sav_next:        std_ulogic;         -- SAV is next
signal xyz_word:        std_ulogic;         -- current word is XYZ word
signal anc_next:        std_ulogic;         -- ANC is next
signal edh_next:        std_ulogic;         -- EDH is next
signal rx_ce:           std_ulogic;         -- clock enable
signal edh_packet:      std_ulogic;         -- edh processor EDH packet indicator
signal packet_flags :   edh_pktflg_type;    -- vector containing the packet error flags listed below
signal edh_missing:     std_ulogic;         -- edh packet was missing
signal edh_parity_err:  std_ulogic;         -- edh packet parity error
signal edh_chksum_err:  std_ulogic;         -- edh packet checksum error
signal edh_format_err:  std_ulogic;         -- edh packet format error
signal rx_ap_flags:     edh_flgset_type;    -- received edh packet AP flags
signal rx_ff_flags:     edh_flgset_type;    -- received edh packet FF flags
signal rx_anc_flags:    edh_flgset_type;    -- recevied edh packet ANC flags
signal ap_flags:        edh_flgset_type;    -- transmitted edh packet AP flags
signal ff_flags:        edh_flgset_type;    -- transmitted edh packet FF flags
signal anc_flags:       edh_flgset_type;    -- transmitted edh packet ANC flags
signal errcnt:          edh_errcnt_type;    -- count of fields containing EDH errors
signal anc_idh_local:   std_ulogic := '0';  -- controls the ANC IDH local input to EDH proc
signal anc_ues_local:   std_ulogic := '0';  -- controls the ANC UES local input to EDH proc
signal ap_idh_local:    std_ulogic := '0';  -- controls the AP IDH local input to EDH proc
signal ff_idh_local:    std_ulogic := '0';  -- controls the FF IDH local input to EDH proc
signal errcnt_flg_en:   edh_allflg_type     -- controls the error count flag enables
            := "1111111111111111";  
signal udw_wr_adr :     udwadr_type         -- UDW RAM write address
            := "00000000";

--
-- This constant defines the number of clock cycles of latency through the
-- anc_edh_processor not including the latency of the video_decoder module.
--
constant LATENCY :        integer := 4;

type dly_bit_type       is array (LATENCY-1 downto 0) of std_ulogic;
type dly_vidstd_type    is array (LATENCY-1 downto 0) of vidstd_type;
type dly_video_type     is array (LATENCY-1 downto 0) of video_type;
type dly_hpos_type      is array (LATENCY-1 downto 0) of hpos_type;
type dly_vpos_type      is array (LATENCY-1 downto 0) of vpos_type;

--
-- These registers delay the output of the decoder by one clock cycle for
-- comparison with the output of the edh_processor module.
--
signal dly_std:         dly_vidstd_type;
signal dly_std_locked:  dly_bit_type;
signal dly_vid:         dly_video_type;
signal dly_f:           dly_bit_type;
signal dly_v:           dly_bit_type;
signal dly_h:           dly_bit_type;
signal dly_hcnt:        dly_hpos_type;
signal dly_vcnt:        dly_vpos_type;
signal dly_sync_switch: dly_bit_type;
signal dly_eav_next:    dly_bit_type;
signal dly_sav_next:    dly_bit_type;
signal dly_xyz_word:    dly_bit_type;
signal dly_anc_next:    dly_bit_type;
signal dly_edh_next:    dly_bit_type;

--
-- These signals control the testbench
--
signal i:                    integer;           -- index into memory array
signal packet:               integer;           -- current received EDH packet number
signal frames:               integer;           -- counts number of frames during test
signal check_flags:          boolean := false;  -- asserted when error flags should be checked
signal expected_rx_ap_flags: edh_flgset_type    -- holds the expected received AP flags value
            := "00000"; 
signal expected_rx_ff_flags: edh_flgset_type    -- holds the expected received FF flags value
            := "00000"; 
signal expected_rx_anc_flags:edh_flgset_type    -- holds the expected receivedANC flags value
            := "00000"; 
signal expected_ap_flags:    edh_flgset_type    -- holds the expected AP flags value
            := "00000"; 
signal expected_ff_flags:    edh_flgset_type    -- holds the expected FF flags value
            := "00000"; 
signal expected_anc_flags:   edh_flgset_type    -- holds the expected ANC flags value
            := "00000"; 
signal expected_chksum_err:  std_ulogic := '0'; -- holds the expected checksum error flag value
signal expected_edh_missing: std_ulogic := '0'; -- holds the expected EDH packet missing flag value
signal expected_parity_err:  std_ulogic := '0'; -- holds the expected parity error flag value
signal expected_format_err:  std_ulogic := '0'; -- holds the expected format error flag value
signal error_found:          boolean := false;              -- asserted when a simulation error is detected


--
-- These signals are targets for init_signal_spy functions that get mapped to
-- signals in the edh_processor module. This is required because you cannot
-- directly reference signals inside a VHDL module from elsewhere in the
-- hierarchy.
--
signal ep_dec_std:          vidstd_type;
signal ep_dec_std_locked:   std_ulogic;
signal ep_dec_vid:          video_type;
signal ep_dec_f:            std_ulogic;
signal ep_dec_v:            std_ulogic;
signal ep_dec_h:            std_ulogic;
signal ep_dec_hcnt:         hpos_type;