anc_demux.vhd

XAPP299 version 1.0 reference design files

        did_d:        in    ubyte_type;     -- DID D value
        sdid_d:       in    ubyte_type;     -- SDID D value
        del_pkt_d:    in    std_ulogic;     -- delete packet when asserted
        data_out:     out   video_type;     -- video output port
        data_out_valid:
                      out   std_ulogic;     -- asserted when data_out contains ANC packet
        match_code:   out                   -- indicates which DID/SDID pair matched packet
            std_ulogic_vector(1 downto 0);
        did:          out   std_ulogic;     -- asserted when DID on data_out
        dbn:          out   std_ulogic;     -- asserted when DBN on data_out
        sdid:         out   std_ulogic;     -- asserted when SDID on data_out
        dc:           out   std_ulogic;     -- asserted when DC on data_out
        udw:          out   std_ulogic;     -- asserted when UDW on data_out
        cs:           out   std_ulogic;     -- asserted when CS on data_out
        vid_out:      out   video_type);    -- output video port
end component;

begin

    --
    -- anc_extract module
    --
    -- This module does all the work of demuxing ANC packets.
    --
    extract: anc_extract
        port map ( 
        clk             => clk,
        ce              => ce,
        rst             => rst,
        anc_next        => in_anc_next,
        vid_in          => vid_in,
        en_a            => en_a,
        did_a           => did_a,
        sdid_a          => sdid_a,
        del_pkt_a       => del_pkt_a,
        en_b            => en_b,
        did_b           => did_b,
        sdid_b          => sdid_b,
        del_pkt_b       => del_pkt_b,
        en_c            => en_c,
        did_c           => did_c,
        sdid_c          => sdid_c,
        del_pkt_c       => del_pkt_c,
        en_d            => en_d,
        did_d           => did_d,
        sdid_d          => sdid_d,
        del_pkt_d       => del_pkt_d,
        data_out        => data_out,
        data_out_valid  => data_out_valid,
        match_code      => match_code,
        did             => did,
        dbn             => dbn,
        sdid            => sdid,
        dc              => dc,
        udw             => udw,
        cs              => cs,
        vid_out         => vid_out);
        
    --
    -- Delay registers for video timing signals
    --
    process(clk, rst)
    begin
        if (rst = '1') then
            trs_dly <= (others => '0');
        elsif (clk'event and clk = '1') then
            if (ce = '1') then
                trs_dly <= (trs_dly(1 downto 0) & in_trs);
            end if;
        end if;
    end process;

    out_trs <= trs_dly(2);

    process(clk, rst)
    begin
        if (rst = '1') then
            f_dly <= (others => '0');
        elsif (clk'event and clk = '1') then
            if (ce = '1') then
                f_dly <= (f_dly(1 downto 0) & in_f);
            end if;
        end if;
    end process;

    out_f <= f_dly(2);

    process(clk, rst)
    begin
        if (rst = '1') then
            v_dly <= (others => '0');
        elsif (clk'event and clk = '1') then
            if (ce = '1') then
                v_dly <= (v_dly(1 downto 0) & in_v);
            end if;
        end if;
    end process;

    out_v <= v_dly(2);

    process(clk, rst)
    begin
        if (rst = '1') then
            h_dly <= (others => '0');
        elsif (clk'event and clk = '1') then
            if (ce = '1') then
                h_dly <= (h_dly(1 downto 0) & in_h);
            end if;
        end if;
    end process;

    out_h <= h_dly(2);

    process(clk, rst)
    begin
        if (rst = '1') then
            hcnt_dly0 <= (others => '0');
            hcnt_dly1 <= (others => '0');
            hcnt_dly2 <= (others => '0');
        elsif (clk'event and clk = '1') then
            if (ce = '1') then
                hcnt_dly0 <= in_hcnt;
                hcnt_dly1 <= hcnt_dly0;
                hcnt_dly2 <= hcnt_dly1;
            end if;
        end if;
    end process;

    out_hcnt <= hcnt_dly2;

    process(clk, rst)
    begin
        if (rst = '1') then
            vcnt_dly0 <= (others => '0');
            vcnt_dly1 <= (others => '0');
            vcnt_dly2 <= (others => '0');
        elsif (clk'event and clk = '1') then
            if (ce = '1') then
                vcnt_dly0 <= in_vcnt;
                vcnt_dly1 <= vcnt_dly0;
                vcnt_dly2 <= vcnt_dly1;
            end if;
        end if;
    end process;

    out_vcnt <= vcnt_dly2;

    process(clk, rst)
    begin
        if (rst = '1') then
            sync_switch_dly <= (others => '0');
        elsif (clk'event and clk = '1') then
            if (ce = '1') then
                sync_switch_dly <= (sync_switch_dly(1 downto 0) & in_sync_switch);
            end if;
        end if;
    end process;

    out_sync_switch <= sync_switch_dly(2);

    process(clk, rst)
    begin
        if (rst = '1') then
            eav_next_dly <= (others => '0');
        elsif (clk'event and clk = '1') then
            if (ce = '1') then
                eav_next_dly <= (eav_next_dly(1 downto 0) & in_eav_next);
            end if;
        end if;
    end process;

    out_eav_next <= eav_next_dly(2);

    process(clk, rst)
    begin
        if (rst = '1') then
            sav_next_dly <= (others => '0');
        elsif (clk'event and clk = '1') then
            if (ce = '1') then
                sav_next_dly <= (sav_next_dly(1 downto 0) & in_sav_next);
            end if;
        end if;
    end process;

    out_sav_next <= sav_next_dly(2);

    process(clk, rst)
    begin
        if (rst = '1') then
            xyz_word_dly <= (others => '0');
        elsif (clk'event and clk = '1') then
            if (ce = '1') then
                xyz_word_dly <= (xyz_word_dly(1 downto 0) & in_xyz_word);
            end if;
        end if;
    end process;

    out_xyz_word <= xyz_word_dly(2);

    process(clk, rst)
    begin
        if (rst = '1') then
            anc_next_dly <= (others => '0');
        elsif (clk'event and clk = '1') then
            if (ce = '1') then
                anc_next_dly <= (anc_next_dly(1 downto 0) & in_anc_next);
            end if;
        end if;
    end process;

    out_anc_next <= anc_next_dly(2);

    process(clk, rst)
    begin
        if (rst = '1') then
            edh_next_dly <= (others => '0');
        elsif (clk'event and clk = '1') then
            if (ce = '1') then
                edh_next_dly <= (edh_next_dly(1 downto 0) & in_edh_next);
            end if;
        end if;
    end process;

    out_edh_next <= edh_next_dly(2);

    process(clk, rst)
    begin
        if (rst = '1') then
            edh_loc_dly <= (others => '0');
        elsif (clk'event and clk = '1') then
            if (ce = '1') then
                edh_loc_dly <= (edh_loc_dly(1 downto 0) & in_edh_loc);
            end if;
        end if;
    end process;

    out_edh_loc <= edh_loc_dly(2);

end synth;