edh_processor.vhd

XAPP299 version 1.0 reference design files

            edh_chksum_err  => edh_chksum_err,
            edh_format_err  => edh_format_err,
            in_ap_flags     => in_ap_flags,
            in_ff_flags     => in_ff_flags,
            in_anc_flags    => in_anc_flags,
            rx_ap_flags     => rx_ap_flags,
            rx_ff_flags     => rx_ff_flags,
            rx_anc_flags    => rx_anc_flags);

    --
    -- edh_loc module
    --
    -- This module locates the beginning of an EDH packet in the incoming video
    -- stream. It asserts the tx_edh_next siganl the sample before the EDH 
    -- packet begins on vid_in.
    --
    LOC : edh_loc
        port map (
            clk             => clk,
            ce              => ce,
            rst             => rst,
            f               => dec_f,
            vcnt            => dec_vcnt,
            hcnt            => dec_hcnt,
            std             => dec_std,
            edh_next        => tx_edh_next);

    --
    -- anc_rx module
    --
    -- This module calculates checksums for every ANC packet in the input video
    -- stream and compares the calculated checksums against the CS word of each
    -- packet. It also checks the parity bits of all parity protected words in 
    -- the ANC packets. An error in any ANC packet will assert the anc_edh_local
    -- signal. This output will remain asserted until after the next EDH packet 
    -- is sent in the output video stream.
    --
    ANCRX : anc_rx
        port map (
            clk             => clk,
            ce              => ce,
            rst             => rst,
            locked          => dec_locked,
            rx_anc_next     => dec_anc_next,
            rx_edh_next     => dec_edh_next,
            edh_packet      => tx_edh_packet,
            vid_in          => dec_vid,
            anc_edh_local   => anc_edh_local);

    --
    -- edh_tx module
    --
    -- This module generates a new EDH packet based on the calculated CRC words
    -- and the incoming and local flags.
    --
    TX : edh_tx
        port map (
            clk             => clk,
            ce              => ce,
            rst             => rst,
            vid_in          => dec_vid,
            edh_next        => tx_edh_next,
            edh_missing     => edh_missing,
            ap_crc_valid    => ap_crc_valid,
            ap_crc          => ap_crc,
            ff_crc_valid    => ff_crc_valid,
            ff_crc          => ff_crc,
            flags_in        => flag_bus,
            ap_flag_word    => ap_flag_word,
            ff_flag_word    => ff_flag_word,
            anc_flag_word   => anc_flag_word,
            edh_packet      => tx_edh_packet,
            edh_vid         => tx_vid_out);


    --
    -- edh_flags module
    --
    -- This module creates the error flags that are included in the new
    -- EDH packet created by the GEN module. It also captures those flags until 
    -- the next EDH packet and provides them as outputs.
    --
    FLAGS : edh_flags 
        port map (
            clk                 => clk,
            ce                  => ce,
            rst                 => rst,
            receive_mode        => receive_mode,
            ap_flag_word        => ap_flag_word,
            ff_flag_word        => ff_flag_word,
            anc_flag_word       => anc_flag_word,
            edh_missing         => edh_missing,
            edh_parity_err      => edh_parity_err,
            edh_format_err      => edh_format_err,
            rx_ap_crc_valid     => rx_ap_crc_valid,
            rx_ap_crc           => rx_ap_crc,
            rx_ff_crc_valid     => rx_ff_crc_valid,
            rx_ff_crc           => rx_ff_crc,
            rx_ap_flags         => in_ap_flags,
            rx_ff_flags         => in_ff_flags,
            rx_anc_flags        => in_anc_flags,
            anc_edh_local       => anc_edh_local,
            anc_idh_local       => anc_idh_local,
            anc_ues_local       => anc_ues_local,
            ap_idh_local        => ap_idh_local,
            ff_idh_local        => ff_idh_local,
            calc_ap_crc_valid   => ap_crc_valid,
            calc_ap_crc         => ap_crc,
            calc_ff_crc_valid   => ff_crc_valid,
            calc_ff_crc         => ff_crc,
            flags               => flag_bus,
            ap_flags            => ap_flags_int,
            ff_flags            => ff_flags_int,
            anc_flags           => anc_flags_int);

    ap_flags <= ap_flags_int;
    ff_flags <= ff_flags_int;
    anc_flags <= anc_flags_int;

        
    --
    -- edh_errcnt module
    --
    -- This counter increments once for every field that contains an enabled 
    -- error. The error counter is disabled until after the video decoder is 
    -- locked to the
    -- video stream for the first time and the first EDH packet has been received.
    --

    edh_all_flags <= (edh_chksum_err & ap_flags_int & ff_flags_int & anc_flags_int);

    ERRCNTR : edh_errcnt
        port map (
            clk                 => clk,
            ce                  => ce,
            rst                 => rst,
            clr_errcnt          => clr_errcnt,
            count_en            => errcnt_en,
            flag_enables        => errcnt_flg_en,
            flags               => edh_all_flags,
            edh_next            => tx_edh_next,
            errcnt              => errcnt);



    process(clk, rst)
    begin
        if (rst = '1') then
            errcnt_en <= '0';
        elsif (clk'event and clk = '1') then
            if (ce = '1') then
                if (dec_locked = '1' and dec_edh_next = '1') then
                    errcnt_en <= '1';
                end if;
            end if;
        end if;
    end process;


    --
    -- packet_flags
    --
    -- This statement combines the four EDH packet flags into a vector.
    --
    packet_flags <= (edh_format_err & edh_chksum_err & edh_parity_err & edh_missing);

    --
    -- output registers
    --
    -- This code implements an output register for the video path and all video
    -- timing signals.
    --
    process(clk, rst)
    begin
        if (rst = '1') then
            vid_out <= (others => '0');
            std <= (others => '0');
            std_locked <= '0';
            trs <= '0';
            field <= '0';
            v_blank <= '0';
            h_blank <= '0';
            horz_count <= (others => '0');
            vert_count <= (others => '0');
            sync_switch <= '0';
            locked <= '0';
            eav_next <= '0';
            sav_next <= '0';
            xyz_word <= '0';
            anc_next <= '0';
            edh_next <= '0';
            edh_packet <= '0';
        elsif (clk'event and clk = '1') then
            if (ce = '1') then
                vid_out <= tx_vid_out;
                std <= dec_std;
                std_locked <= dec_std_locked;
                trs <= dec_trs;
                field <= dec_f;
                v_blank <= dec_v;
                h_blank <= dec_h;
                horz_count <= dec_hcnt;
                vert_count <= dec_vcnt;
                sync_switch <= dec_sync_switch;
                locked <= dec_locked;
                eav_next <= dec_eav_next;
                sav_next <= dec_sav_next;
                xyz_word <= dec_xyz_word;
                anc_next <= dec_anc_next;
                edh_next <= dec_edh_next;
                edh_packet <= tx_edh_packet;
            end if; 
        end if;
    end process;

end synth;