edh_processor.vhd

XAPP299 version 1.0 reference design files

end component;

component edh_crc
    port (
        clk:            in  std_ulogic;         -- clock input
        ce:             in  std_ulogic;         -- clock enable
        rst:            in  std_ulogic;         -- async reset input
        f:              in  std_ulogic;         -- field bit
        h:              in  std_ulogic;         -- horizontal blanking bit
        eav_next:       in  std_ulogic;         -- asserted when next samplebegins EAV symbol
        xyz_word:       in  std_ulogic;         -- asserted when current word is the XYZ word of a TRS
        vid_in:         in  video_type;         -- video data
        vcnt:           in  vpos_type;          -- vertical line count
        std:            in  vidstd_type;        -- indicates the video standard
        locked:         in  std_ulogic;         -- asserted when flywheel is locked
        ap_crc:         out crc16_type;         -- calculated active picture CRC
        ap_crc_valid:   out std_ulogic;         -- asserted when AP CRC is valid
        ff_crc:         out crc16_type;         -- calculated full-frame CRC
        ff_crc_valid:   out std_ulogic);        -- asserted when FF CRC is valid
end component;

component edh_rx
    port (
        clk:            in  std_ulogic;         -- clock input
        ce:             in  std_ulogic;         -- clock enable
        rst:            in  std_ulogic;         -- async reset input
        rx_edh_next:    in  std_ulogic;         -- indicates the next word is the first word of a received EDH packet
        vid_in:         in  video_type;         -- video data
        edh_next:       in  std_ulogic;         -- EDH packet begins on next sample
        reg_flags:      in  std_ulogic;         -- 1 = register flag words, 0 = feed vid_in through
        ap_crc_valid:   out std_ulogic;         -- valid bit for active picture CRC
        ap_crc:         out crc16_type;         -- active picture CRC
        ff_crc_valid:   out std_ulogic;         -- valid bit for full field CRC
        ff_crc:         out crc16_type;         -- full field CRC
        edh_missing:    out std_ulogic;         -- asserted when last expected EDH packet was missing
        edh_parity_err: out std_ulogic;         -- asserted when a parity error occurs in EDH packet
        edh_chksum_err: out std_ulogic;         -- asserted when a checksum error occurs in EDH packet
        edh_format_err: out std_ulogic;         -- asserted when a format error is found in EDH packet
        in_ap_flags:    out edh_flgset_type;    -- received AP flag word to edh_flags module
        in_ff_flags:    out edh_flgset_type;    -- received FF flag word to edh_flags module
        in_anc_flags:   out edh_flgset_type;    -- received ANC flag word to edh_flags module
        rx_ap_flags:    out edh_flgset_type;    -- received & registered AP flags for external inspection
        rx_ff_flags:    out edh_flgset_type;    -- received & registered FF flags for external inspection
        rx_anc_flags:   out edh_flgset_type);   -- received & registered ANC flags for external inspection
end component;

component edh_loc
    port (
        clk:            in  std_ulogic;         -- clock input
        ce:             in  std_ulogic;         -- clock enable
        rst:            in  std_ulogic;         -- async reset input
        f:              in  std_ulogic;         -- field bit
        vcnt:           in  vpos_type;          -- vertical line count
        hcnt:           in  hpos_type;          -- horizontal position
        std:            in  vidstd_type;        -- video standards
        edh_next:       out std_ulogic);        -- EDH packet should begin on next sample
end component;

component anc_rx
    port (
        clk:            in  std_ulogic;         -- clock input
        ce:             in  std_ulogic;         -- clock enable
        rst:            in  std_ulogic;         -- async reset input
        locked:         in  std_ulogic;         -- video decoder locked signal
        rx_anc_next:    in  std_ulogic;         -- asserted when next word begins ANC packet
        rx_edh_next:    in  std_ulogic;         -- asserted when next word begins EDH packet
        edh_packet:     in  std_ulogic;         -- indicates an EDH packet is being generated
        vid_in:         in  video_type;         -- video input data
        anc_edh_local:  out std_ulogic);        -- ANC error detected here flag
end component;

component edh_tx
    port (
        clk:            in  std_ulogic;         -- clock input
        ce:             in  std_ulogic;         -- clock enable
        rst:            in  std_ulogic;         -- async reset input
        vid_in:         in  video_type;         -- input video port
        edh_next:       in  std_ulogic;         -- asserted when next sample begins EDH packet
        edh_missing:    in  std_ulogic;         -- receved EDh packet is missing
        ap_crc_valid:   in  std_ulogic;         -- asserted when AP CRC is valid
        ap_crc:         in  crc16_type;         -- calculated active picture CRC
        ff_crc_valid:   in  std_ulogic;         -- asserted when FF CRC is valid
        ff_crc:         in  crc16_type;         -- calculated full-frame CRC
        flags_in:       in  edh_flgset_type;    -- bus that carries AP, FF, and ANC flags
        ap_flag_word:   out std_ulogic;         -- asserted during AP flag word in EDH packet
        ff_flag_word:   out std_ulogic;         -- asserted during FF flag word in EDH packet
        anc_flag_word:  out std_ulogic;         -- asserted during ANC flag word in EDH packet
        edh_packet:     out std_ulogic;         -- asserted during all words of EDH packet
        edh_vid:        out video_type);        -- generated EDH packet data
end component;

component edh_flags
    port (
        clk:                in  std_ulogic;     -- clock input
        ce:                 in  std_ulogic;     -- clock enable
        rst:                in  std_ulogic;     -- async reset input
        receive_mode:       in  std_ulogic;     -- asserted if receiver is active
        ap_flag_word:       in  std_ulogic;     -- selects the AP flag word for flag_bus
        ff_flag_word:       in  std_ulogic;     -- selects the FF flag word for flag_bus
        anc_flag_word:      in  std_ulogic;     -- selects the ANC flag word for the flag_bus
        edh_missing:        in  std_ulogic;     -- EDH packet missing from data stream
        edh_parity_err:     in  std_ulogic;     -- EDH packet parity error
        edh_format_err:     in  std_ulogic;     -- EDH packet format error
        rx_ap_crc_valid:    in  std_ulogic;     -- received AP CRC valid bit
        rx_ap_crc:          in  crc16_type;     -- received AP CRC value 
        rx_ff_crc_valid:    in  std_ulogic;     -- received FF CRC valid bit
        rx_ff_crc:          in  crc16_type;     -- received FF CRC value
        rx_ap_flags:        in  edh_flgset_type;-- received AP flag word
        rx_ff_flags:        in  edh_flgset_type;-- received FF flag word
        rx_anc_flags:       in  edh_flgset_type;-- recevied ANC flag word
        anc_edh_local:      in  std_ulogic;     -- local ANC EDH flag input
        anc_idh_local:      in  std_ulogic;     -- local ANC IDH flag input
        anc_ues_local:      in  std_ulogic;     -- local ANC UES flag input
        ap_idh_local:       in  std_ulogic;     -- local AP IDH flag input
        ff_idh_local:       in  std_ulogic;     -- local FF IDH flag input
        calc_ap_crc_valid:  in  std_ulogic;     -- calculated AP CRC valid bit
        calc_ap_crc:        in  crc16_type;     -- calculated AP CRC value
        calc_ff_crc_valid:  in  std_ulogic;     -- calculated FF CRC value
        calc_ff_crc:        in  crc16_type;     -- calculated FF CRC
        flags:              out edh_flgset_type;-- flag bus output
        ap_flags:           out edh_flgset_type;-- AP flags from last EDH packet sent
        ff_flags:           out edh_flgset_type;-- FF flags from last EDH packet sent
        anc_flags:          out edh_flgset_type);-- ANC flags from last EDH packet sent
end component;

component edh_errcnt
    port (
        clk:            in    std_ulogic;       -- clock input
        ce:             in    std_ulogic;       -- clock enable
        rst:            in    std_ulogic;       -- async reset input
        clr_errcnt:     in    std_ulogic;       -- clears the error counter
        count_en:       in    std_ulogic;       -- enables error counter when high
        flag_enables:   in    edh_allflg_type;  -- specifies which error flags cause the counter to increment
        flags:          in    edh_allflg_type;  -- error flag inputs
        edh_next:       in    std_ulogic;       -- counter increment on edh_next asserted
        errcnt:         out   edh_errcnt_type); -- errored field counter
end component;

begin
    
    --
    -- Instantiate video decoder module from XAPP625
    --
    DEC : video_decode
        port map (
            clk             => clk,
            ce              => ce,
            rst             => rst,
            vid_in          => vid_in,
            reacquire       => reacquire,
            en_sync_switch  => en_sync_switch,
            en_trs_blank    => en_trs_blank,
            std             => dec_std,
            std_locked      => dec_std_locked,
            trs             => dec_trs,
            vid_out         => dec_vid,
            field           => dec_f,
            v_blank         => dec_v,
            h_blank         => dec_h,
            horz_count      => dec_hcnt,
            vert_count      => dec_vcnt,
            sync_switch     => dec_sync_switch,
            locked          => dec_locked,
            eav_next        => dec_eav_next,
            sav_next        => dec_sav_next,
            xyz_word        => dec_xyz_word,
            anc_next        => dec_anc_next,
            edh_next        => dec_edh_next);

    --
    -- edh_crc module
    --
    -- This module computes the CRC values for the incoming video stream, vid_in.
    -- Also, the module generates valid signals for both CRC values based on the
    -- locked signal. If locked rises during a field, the CRC is considered to 
    -- be invalid.
    --
    CRC : edh_crc
        port map (
            clk             => clk,
            ce              => ce,
            rst             => rst,
            f               => dec_f,
            h               => dec_h,
            eav_next        => dec_eav_next,
            xyz_word        => dec_xyz_word,
            vid_in          => dec_vid,
            vcnt            => dec_vcnt,
            std             => dec_std,
            locked          => dec_locked,
            ap_crc          => ap_crc,
            ap_crc_valid    => ap_crc_valid,
            ff_crc          => ff_crc,
            ff_crc_valid    => ff_crc_valid);

    --
    -- edh_rx module
    --
    -- This module processes EDH packets found in the incoming video stream. The
    -- CRC words and valid flags are captured from the packet. Various error 
    -- flags related to errors found in the packet are generated.
    --
    EDHRX : edh_rx
        port map (
            clk             => clk,
            ce              => ce,
            rst             => rst,
            rx_edh_next     => dec_edh_next,
            vid_in          => dec_vid,
            edh_next        => tx_edh_next,
            reg_flags       => GND,
            ap_crc_valid    => rx_ap_crc_valid,
            ap_crc          => rx_ap_crc,
            ff_crc_valid    => rx_ff_crc_valid,
            ff_crc          => rx_ff_crc,
            edh_missing     => edh_missing,
            edh_parity_err  => edh_parity_err,