edh_crc.vhd

XAPP299 version 1.0 reference design files

    --
    -- ap_region and ff_region generation
    -- 
    -- This code determines when the current video signal is within the active
    -- picture and full field CRC regions. Note that since the F bit changes 
    -- before the end of the EDH full-field time period, the ff_end_line value 
    -- is set to the opposite field value in the assignments below. That is, if 
    -- F is low, normally indicating Field 1, the ff_end_line is assigned to 
    -- xxx_FLD2_FF_LAST, not xxx_FLD1_FF_LAST as might be expected.
    --

    -- This section looks up the starting and ending line numbers of the two CRC
    -- regions based on the current field and video standard.
    process(ntsc, f)
    begin
        if (ntsc = '1') then
            if (f = '0') then
                ap_start_line <= NTSC_FLD1_AP_FIRST;
                ap_end_line   <= NTSC_FLD1_AP_LAST;
                ff_start_line <= NTSC_FLD1_FF_FIRST;
                ff_end_line   <= NTSC_FLD2_FF_LAST;
            else
                ap_start_line <= NTSC_FLD2_AP_FIRST;
                ap_end_line   <= NTSC_FLD2_AP_LAST;
                ff_start_line <= NTSC_FLD2_FF_FIRST;
                ff_end_line   <= NTSC_FLD1_FF_LAST;
            end if;
        else
            if (f = '0') then
                ap_start_line <= PAL_FLD1_AP_FIRST;
                ap_end_line   <= PAL_FLD1_AP_LAST;
                ff_start_line <= PAL_FLD1_FF_FIRST;
                ff_end_line   <= PAL_FLD2_FF_LAST;
            else
                ap_start_line <= PAL_FLD2_AP_FIRST;
                ap_end_line   <= PAL_FLD2_AP_LAST;
                ff_start_line <= PAL_FLD2_FF_FIRST;
                ff_end_line   <= PAL_FLD1_FF_LAST;
            end if;
        end if;
    end process;

    -- These four statements compare the current vcnt value to the starting and
    -- ending line numbers of the two CRC regions.          
    ap_start <= '1' when vcnt = ap_start_line else '0';
    ap_end   <= '1' when vcnt = ap_end_line else '0';
    ff_start <= '1' when vcnt = ff_start_line else '0';
    ff_end   <= '1' when vcnt = ff_end_line else '0';

    -- This code block generates the ap_region signal indicating when the 
    -- current position is in the active-picture CRC region.
    ap_crc_clr <= ap_start and xyz_word and sav;

    process(clk, rst)
    begin
        if (rst = '1') then
            ap_region <= '0';
        elsif (clk'event and clk = '1') then
            if (ce = '1') then
                if (ap_crc_clr = '1') then
                    ap_region <= '1';
                elsif (ap_end = '1' and eav_next = '1') then
                    ap_region <= '0';
                end if;
            end if;
        end if;
    end process;


    -- This code block generates teh ff_region signal indicating when the 
    -- current position is in the full-field CRC region.
    ff_crc_clr <= ff_start and xyz_word and eav;

    process(clk, rst)
    begin
        if (rst = '1') then
            ff_region <= '0';
        elsif (clk'event and clk = '1') then
            if (ce = '1') then
                if (ff_crc_clr = '1') then
                    ff_region <= '1';
                elsif (ff_end = '1' and eav_next = '1') then
                    ff_region <= '0';
                end if;
            end if;
        end if;
    end process;

    --
    -- Valid bit generation
    --
    -- This code generates the two CRC valid bits.
    --
    process(clk, rst)
    begin
        if (rst = '1') then
            prev_locked <= '0';
        elsif (clk'event and clk = '1') then
            if (ce = '1') then
                prev_locked <= locked;
            end if;
        end if;
    end process;

    locked_rise <= not prev_locked and locked;

    process(clk, rst)
    begin
        if (rst = '1') then
            ap_valid <= '0';
        elsif (clk'event and clk = '1') then
            if (ce = '1') then
                if (locked_rise = '1') then
                    ap_valid <= '0';
                elsif (locked = '1' and ap_crc_clr = '1') then
                    ap_valid <= '1';
                end if;
            end if;
        end if;
    end process;

    process(clk, rst)
    begin
        if (rst = '1') then
            ff_valid <= '0';
        elsif (clk'event and clk = '1') then
            if (ce = '1') then
                if (locked_rise = '1') then
                    ff_valid <= '0';
                elsif (locked = '1' and ff_crc_clr = '1') then
                    ff_valid <= '1';
                end if;
            end if;
        end if;
    end process;

    --
    -- CRC calculations and registers
    --
    -- Each CRC is calculated separately by an edh_crc16 module. Associted with
    -- each is a register. The register acts as an accumulation register and is
    -- fed back into the edh_crc16 module to be combined with the next video
    -- word. Enable logic for the registers determines which words are 
    -- accumulated into the CRC value by controlling the load enables to the two
    -- registers.
    --

    -- Active-picture CRC calculator
    apcrc16 : edh_crc16
        port map (
            c       => ap_crc_reg,
            d       => clipped_vid,
            crc     => ap_crc16);

    -- Active-picture CRC register
    process(clk, rst)
    begin
        if (rst = '1') then
            ap_crc_reg <= (others => '0');
        elsif (clk'event and clk = '1') then
            if (ce = '1') then
                if (ap_crc_clr = '1') then
                    ap_crc_reg <= (others => '0');
                elsif (ap_region = '1' and h = '0') then
                    ap_crc_reg <= ap_crc16;
                end if;
            end if;
        end if;
    end process;
            
    -- Full-field CRC calculator
    ffcrc16 : edh_crc16
        port map (
            c       => ff_crc_reg,
            d       => clipped_vid,
            crc     => ff_crc16);

    -- Full-field CRC register
    process(clk, rst)
    begin
        if (rst = '1') then
            ff_crc_reg <= (others => '0');
        elsif (clk'event and clk = '1') then
            if (ce = '1') then
                if (ff_crc_clr = '1') then
                    ff_crc_reg <= (others => '0');
                elsif (ff_region = '1') then
                    ff_crc_reg <= ff_crc16;
                end if;
            end if;
        end if;
    end process;
            
    --
    -- Output assignments
    --
    ap_crc <= ap_crc_reg;
    ap_crc_valid <= ap_valid;
    ff_crc <= ff_crc_reg;
    ff_crc_valid <= ff_valid;
                        
end synth;