edh_crc.vhd

XAPP299 version 1.0 reference design files

--------------------------------------------------------------------------------
-- edh_crc.vhd
--
-- SDI EDH CRC generator
--
--
--
--                  Author: John F. Snow
--                  Staff Applications Engineer
--
--                  Video Applications
--                  Advanced Products Group
--                  Xilinx, Inc.
--
--                  Copyright (c) 2002 Xilinx, Inc.
--                  All rights reserved
--
--                  Date:   May 8, 2002
--
--                  RESTRICTED RIGHTS LEGEND
--
--      This software has not been published by the author, and 
--      has been disclosed to others for the purpose of enhancing 
--      and promoting design productivity in Xilinx products.
--
--      Therefore use, duplication or disclosure, now and in the 
--      future should give consideration to the productivity 
--      enhancements afforded the user of this code by the author's 
--      efforts.  Thank you for using our products !
--
-- Disclaimer:  THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY 
--              WHATSOEVER AND XILINX SPECIFICALLY DISCLAIMS ANY 
--              IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
--              A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
--
-- Revision:
--              May 8, 2002     Release
--
-- Other modules instanced in this design:
--          edh_crc16
--
--------------------------------------------------------------------------------
-- 
-- This module calculates the active picture and full-frame CRC values. The 
-- ITU-R BT.1304 and SMPTE RP 165-1994 standards define how the two CRC values 
-- are to be calculated.
-- 
-- The module uses the vertical line count (vcnt) input, the field bit (f), the
-- horizontal blanking interval bit (h), and the eav_next, sav_next, and 
-- xyz_word inputs to determine which samples to include in the two CRC 
-- calculations.
-- 
-- The calculation is a standard CRC16 calculation with a polynomial of x^16 + 
-- x^12 + x^5 + 1. The function considers the LSB of the video data as the first
-- bit shifted into the CRC generator, although the implementation given here is
-- a fully parallel CRC, calculating all 16 CRC bits from the 10-bit video data 
-- in one clock cycle.  The CRC calculation is done is the edh_crc16 module. It 
-- is  instanced twice, once for the full-frame calculation and once for the 
-- active-picture calculation.    
-- 
-- For each CRC calculation, a valid bit is also generated. After reset the 
-- valid bits will be negated until the locked input from the video decoder is 
-- asserted. The valid bits remain asserted even if locked is negated. However, 
-- the valid bits will be negated for one filed if the locked signal rises 
-- during a CRC calculation, indicating that the video decoder has 
-- re-synchronized.
--

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;

use work.anc_edh_pkg.all;

entity edh_crc is
    port (
        -- inputs
        clk:            in  std_ulogic; -- clock input
        ce:             in  std_ulogic; -- clock enable
        rst:            in  std_ulogic; -- async reset input
        f:              in  std_ulogic; -- field bit
        h:              in  std_ulogic; -- horizontal blanking bit
        eav_next:       in  std_ulogic; -- asserted when next samplebegins EAV symbol
        xyz_word:       in  std_ulogic; -- asserted when current word is the XYZ word of a TRS
        vid_in:         in  video_type; -- video data
        vcnt:           in  vpos_type;  -- vertical line count
        std:            in  vidstd_type;-- indicates the video standard
        locked:         in  std_ulogic; -- asserted when flywheel is locked

        -- outputs
        ap_crc:         out crc16_type; -- calculated active picture CRC
        ap_crc_valid:   out std_ulogic; -- asserted when AP CRC is valid
        ff_crc:         out crc16_type; -- calculated full-frame CRC
        ff_crc_valid:   out std_ulogic);-- asserted when FF CRC is valid
end;


architecture synth of edh_crc is

--------------------------------------------------------------------------------
-- Constant definitions
--

--
-- This group of constants defines the line numbers that begin and end the
-- two CRC intervals. Values are given for both fields and for both NTSC and
-- PAL.
--
constant NTSC_FLD1_AP_FIRST: vpos_type := vpos_type(TO_UNSIGNED( 21, vpos_type'length));
constant NTSC_FLD1_AP_LAST:  vpos_type := vpos_type(TO_UNSIGNED(262, vpos_type'length));
constant NTSC_FLD1_FF_FIRST: vpos_type := vpos_type(TO_UNSIGNED( 12, vpos_type'length));
constant NTSC_FLD1_FF_LAST:  vpos_type := vpos_type(TO_UNSIGNED(271, vpos_type'length));
    
constant NTSC_FLD2_AP_FIRST: vpos_type := vpos_type(TO_UNSIGNED(284, vpos_type'length));
constant NTSC_FLD2_AP_LAST:  vpos_type := vpos_type(TO_UNSIGNED(525, vpos_type'length));
constant NTSC_FLD2_FF_FIRST: vpos_type := vpos_type(TO_UNSIGNED(275, vpos_type'length));
constant NTSC_FLD2_FF_LAST:  vpos_type := vpos_type(TO_UNSIGNED(  8, vpos_type'length));

constant PAL_FLD1_AP_FIRST:  vpos_type := vpos_type(TO_UNSIGNED( 24, vpos_type'length));
constant PAL_FLD1_AP_LAST:   vpos_type := vpos_type(TO_UNSIGNED(310, vpos_type'length));
constant PAL_FLD1_FF_FIRST:  vpos_type := vpos_type(TO_UNSIGNED(  8, vpos_type'length));
constant PAL_FLD1_FF_LAST:   vpos_type := vpos_type(TO_UNSIGNED(317, vpos_type'length));

constant PAL_FLD2_AP_FIRST:  vpos_type := vpos_type(TO_UNSIGNED(336, vpos_type'length));
constant PAL_FLD2_AP_LASt:   vpos_type := vpos_type(TO_UNSIGNED(622, vpos_type'length));
constant PAL_FLD2_FF_FIRST:  vpos_type := vpos_type(TO_UNSIGNED(321, vpos_type'length));
constant PAL_FLD2_FF_LAST:   vpos_type := vpos_type(TO_UNSIGNED(  4, vpos_type'length));


-------------------------------------------------------------------------------
-- Signal defintions
--
signal ntsc:            std_ulogic;     -- 1 = NTSC, 0 = PAL
signal ap_crc_reg:      crc16_type;     -- active picture CRC register
signal ff_crc_reg:      crc16_type;     -- full field cRC register
signal ap_crc16:        crc16_type;     -- active picture CRC calc output
signal ff_crc16:        crc16_type;     -- full field CRC calc output
signal ap_region:       std_ulogic;     -- asserted during active picture CRC interval
signal ff_region:       std_ulogic;     -- asserted during full field CRC interval
signal ap_start_line:   vpos_type;      -- active picture interval start line
signal ap_end_line:     vpos_type;      -- active picture interval end line
signal ff_start_line:   vpos_type;      -- full field interval start line
signal ff_end_line:     vpos_type;      -- full field interval end line
signal ap_start:        std_ulogic;     -- result of comparing ap_start_line with vcnt
signal ap_end:          std_ulogic;     -- result of comparing ap_end_line with vcnt
signal ff_start:        std_ulogic;     -- result of comparing ff_start_line with vcnt
signal ff_end:          std_ulogic;     -- result of comparing ff_end_line with vcnt
signal sav:             std_ulogic;     -- asserted during XYZ word of SAV symbol
signal eav:             std_ulogic;     -- asserted during XYZ word of EAV symbol
signal ap_crc_clr:      std_ulogic;     -- clears the active picture CRC register
signal ff_crc_clr:      std_ulogic;     -- clears the full field CRC register
signal clipped_vid:     video_type;     -- output of video clipper function
signal ap_valid:        std_ulogic;     -- ap_crc_valid internal signal
signal ff_valid:        std_ulogic;     -- ff_crc_valid internal signal
signal prev_locked:     std_ulogic;     -- locked input signal delayed once clock
signal locked_rise:     std_ulogic;     -- asserted on rising edge of locked
signal clip:            std_ulogic;     -- clip the input video when asserted

--
-- Component definitions
--
component edh_crc16
    port(
        c:      in    crc16_type;       -- current CRC value
        d:      in    video_type;       -- input data word
        crc:    inout crc16_type);      -- new calculated CRC value
end component;
    
begin
    
    --
    -- video clipper
    --
    -- The SMPTE and ITU specifications require that the video data values used
    -- by the CRC calculation have the 2 LSBs both be ones if the 8 MSBs are all
    -- ones.
    --
    clip <= vid_in(9) and vid_in(8) and vid_in(7) and vid_in(6) and
            vid_in(5) and vid_in(4) and vid_in(3) and vid_in(2);

    process(clip, vid_in)
    begin
        clipped_vid(9 downto 2) <= vid_in(9 downto 2);
        if (clip = '1') then
            clipped_vid(1 downto 0) <= "11";
        else
            clipped_vid(1 downto 0) <= vid_in(1 downto 0);
        end if;
    end process;

    --
    -- decoding
    --
    -- These assignments generate the ntsc, eav, and sav signals.
    --
    ntsc <= '1' when (std = NTSC_422 or std = NTSC_INVALID or
                      std = NTSC_422_WIDE or std = NTSC_4444) else '0';
                       
    sav <= not vid_in(6) and xyz_word;
    eav <= vid_in(6) and xyz_word;