test_edh.vhd

XAPP299 version 1.0 reference design files

signal ep_anc_flags:        edh_flgset_type;
signal ep_ap_flags:         edh_flgset_type;
signal ep_ff_flags:         edh_flgset_type;

signal VCC :                std_ulogic := '1';
signal GND :                std_ulogic := '0';

component edh_processor
    port (
        clk:            in  std_ulogic;     
        ce:             in  std_ulogic;     
        rst:            in  std_ulogic;     

        -- video decoder inputs
        vid_in:         in  video_type;     
        reacquire:      in  std_ulogic;     
        en_sync_switch: in  std_ulogic;     
        en_trs_blank:   in  std_ulogic;     

        -- EDH flag inputs
        anc_idh_local:  in  std_ulogic;     
        anc_ues_local:  in  std_ulogic;     
        ap_idh_local:   in  std_ulogic;     
        ff_idh_local:   in  std_ulogic;     
        errcnt_flg_en:  in  edh_allflg_type;
        clr_errcnt:     in  std_ulogic;     
        receive_mode:   in  std_ulogic;     

        -- video and decoded video timing outputs
        vid_out:        out video_type;     
        std:            out vidstd_type;    
        std_locked:     out std_ulogic;     
        trs:            out std_ulogic;     
        field:          out std_ulogic;     
        v_blank:        out std_ulogic;     
        h_blank:        out std_ulogic;     
        horz_count:     out hpos_type;      
        vert_count:     out vpos_type;      
        sync_switch:    out std_ulogic;     
        locked:         out std_ulogic;     
        eav_next:       out std_ulogic;     
        sav_next:       out std_ulogic;     
        xyz_word:       out std_ulogic;     
        anc_next:       out std_ulogic;     
        edh_next:       out std_ulogic;     

        -- EDH flag outputs
        rx_ap_flags:    out edh_flgset_type;
        rx_ff_flags:    out edh_flgset_type;
        rx_anc_flags:   out edh_flgset_type;
        ap_flags:       out edh_flgset_type;
        ff_flags:       out edh_flgset_type;
        anc_flags:      out edh_flgset_type;
        packet_flags:   out edh_pktflg_type;
        errcnt:         out edh_errcnt_type;
        edh_packet:     out std_ulogic);    
end component;


--
-- Checksum function
--
function calc_parity(d : std_ulogic_vector(7 downto 0)) return std_ulogic is
begin
    return (d(7) xor d(6) xor d(5) xor d(4) xor d(3) xor d(2) xor d(1) xor d(0));   
end calc_parity;            

begin
    
    --
    -- Map some internal signals to the signals at the top level of the
    -- testbench so they can be used as reference signals.
    --
    process
    begin
        init_signal_spy("/U1/dec_std", "/ep_dec_std", 0);
        init_signal_spy("/U1/dec_std_locked", "/ep_dec_std_locked", 0);
        init_signal_spy("/U1/dec_vid", "/ep_dec_vid", 0);
        init_signal_spy("/U1/dec_f", "/ep_dec_f", 0);
        init_signal_spy("/U1/dec_v", "/ep_dec_v", 0);
        init_signal_spy("/U1/dec_h", "/ep_dec_h", 0);
        init_signal_spy("/U1/dec_hcnt", "/ep_dec_hcnt", 0);
        init_signal_spy("/U1/dec_vcnt", "/ep_dec_vcnt", 0);
        init_signal_spy("/U1/dec_sync_switch", "/ep_dec_sync_switch", 0);
        init_signal_spy("/U1/dec_locked", "/ep_dec_locked", 0);
        init_signal_spy("/U1/dec_eav_next", "/ep_dec_eav_next", 0);
        init_signal_spy("/U1/dec_sav_next", "/ep_dec_sav_next", 0);
        init_signal_spy("/U1/dec_xyz_word", "/ep_dec_xyz_word", 0);
        init_signal_spy("/U1/dec_anc_next", "/ep_dec_anc_next", 0);
        init_signal_spy("/U1/dec_edh_next", "/ep_dec_edh_next", 0);
        init_signal_spy("/U1/ap_crc", "/ep_ap_crc", 0);
        init_signal_spy("/U1/ap_crc_valid", "/ep_ap_crc_valid", 0);
        init_signal_spy("/U1/ff_crc", "/ep_ff_crc", 0);
        init_signal_spy("/U1/ff_crc_valid", "/ep_ff_crc_valid", 0);
        init_signal_spy("/U1/anc_flags", "/ep_anc_flags", 0);
        init_signal_spy("/U1/ap_flags", "/ep_ap_flags", 0);
        init_signal_spy("/U1/ff_flags", "/ep_ff_flags", 0);
        wait;
    end process;

    --
    -- Instantiate the video processor module
    --
    U1 : edh_processor
        port map (
            clk             => clk,
            ce              => rx_ce,
            rst             => rst,
            vid_in          => vid_in,
            reacquire       => GND,
            en_sync_switch  => VCC,
            en_trs_blank    => VCC,
            anc_idh_local   => anc_idh_local,
            anc_ues_local   => anc_ues_local,
            ap_idh_local    => ap_idh_local,
            ff_idh_local    => ff_idh_local,
            errcnt_flg_en   => errcnt_flg_en,
            clr_errcnt      => GND,
            receive_mode    => VCC,
            std             => std,
            std_locked      => std_locked,
            trs             => trs,
            vid_out         => vid_out,
            field           => f,
            v_blank         => v,
            h_blank         => h,
            horz_count      => hcnt,
            vert_count      => vcnt,
            sync_switch     => sync_switch,
            locked          => locked,
            eav_next        => eav_next,
            sav_next        => sav_next,
            xyz_word        => xyz_word,
            anc_next        => anc_next,
            edh_next        => edh_next,
            rx_ap_flags     => rx_ap_flags,
            rx_ff_flags     => rx_ff_flags,
            rx_anc_flags    => rx_anc_flags,
            ap_flags        => ap_flags,
            ff_flags        => ff_flags,
            anc_flags       => anc_flags,
            packet_flags    => packet_flags,
            errcnt          => errcnt,
            edh_packet      => edh_packet);

    edh_format_err <= packet_flags(3);
    edh_chksum_err <= packet_flags(2);
    edh_parity_err <= packet_flags(1);
    edh_missing    <= packet_flags(0);

    --
    -- Read in one frame of NTSC video into memory array
    --
    process
    file     infile:    TEXT open read_mode is "C:/work/XAPP299/sim/one_frame.txt";
    variable buf:       line;
    variable data:      std_logic_vector(11 downto 0);
    variable words:     integer := 0;
    variable good:      boolean;
     
    begin
        while not (endfile(infile)) loop
            readline(infile, buf);              -- read a line from file into buffer
            for i in 0 to 15 loop               -- there are 16 words per line in the file
                exit when words = MAX_MEM;      -- last line doesn't contain 16 words so put an early escape mechanism here
                hread(buf, data, good);         -- read one word from the buffer
                assert good                     -- make sure the read was OK
                    report "Text I/O read error"
                    severity failure;
                memory(words) := video_type(data(9 downto 0));  -- write word to the memory array
                words := words + 1;
            end loop;
        end loop;
        wait;   
    end process;

    --
    -- Generate a clock signal at 27 MHz.
    --
    clk <= enclk and not clk after 18.5 ns;
    rx_ce <= '1';

    --
    -- Assert the reset signal for the first few clock cycles
    --
        process
        begin
            for count in 1 to 5 loop
                wait until clk'event and clk = '0';
            end loop;
            rst <= '0';
            wait;
        end process;

    --
    -- This code keeps track of the number of EDH packets received. Packets received
    -- before the video decoder locks are not counted.
    --
    process
    begin
        packet <= 0;
        
        -- Wait for video decoder to lock to video  
        wait until rst = '0' and locked = '1';

        -- Increment the EDH packet number at each received packet
        loop
            wait until edh_packet'event and edh_packet = '1';
            packet <= packet + 1;
        end loop;
    end process;

    --
    -- This code generates the index into the memory array and the frame counter.
    -- The index begins at a negative number. When the index is negative, no video
    -- is generated. A few cycles with no video are used to make sure the modules
    -- come out of reset before the test set is sent. When the index reaches the
    -- maximum size of the memory array, it is reset to zero and the frame counter
    -- is incremented.
    --

    process(clk, rst)
    begin
        if (rst = '1') then
            i <= -5;
            frames <= 0;
        elsif (clk'event and clk = '1') then
            if (i = MAX_MEM - 1 and frames < 8) then
                i <= 0;
                frames <= frames + 1;
            else
                i <= i + 1;
            end if;
        end if; 
    end process;

    --
    -- Whenever the memory index changes, look up a new video data value from the
    -- memory array and assign that value to d.
    --
    process(i)
    begin
        if (i < 0 or i >= MAX_MEM or frames > 7) then
            d <= (others => '0');
        else
            d <= memory(i);
        end if;
    end process;

    --
    -- When the frame counter changes, this is executed to set up frame specific
    -- values. For the first four frames, all error counter enable flags are
    -- asserted. For the last four frames, only the AP and FF EDH and EDA flags
    -- will cause the error counter to increment. When the frame counter reaches 8,
    -- the test stops.
    -- 
    process(frames)
        variable l : line;
        variable success_string :       string (1 to 28) 
                                        := "Test completed successfully.";
        variable error_string :         string (1 to 40)
                                        := "Expected 7 fields with errors, received ";
    begin
        if (frames >= 4) then
            errcnt_flg_en <= "0000110001100000";    -- 0x0c60
        end if;

        if (frames = 8) then
            
            if (errcnt = 7 and not error_found) then
                write(l, success_string);
                writeline(output, l); 
            else
                write(l, error_string);
                write(l, errcnt);
                writeline(output, l);           
            end if;