test_anc_mux.vhd

XAPP299 version 1.0 reference design files

        wait until (clk'event and clk = '0');
        
        -- Line 5: Insert a 225-word HANC packet on line 5.
        anc_in <= ("00" & LINE5_DC);
        ld_dc <= '1';
        wait until (clk'event and clk = '0');
        ld_dc <= '0';
        pkt_rdy_in <= '1';

        wait until (pkt_in_empty'event and pkt_in_empty = '0');
        wait until (clk'event and clk = '0');
        pkt_rdy_in <= '0';

        wait until (pkt_in_empty'event and pkt_in_empty = '1');
        wait until (clk'event and clk = '0');

        -- Line 6: Insert a 23-word HANC packet on line 6.
        anc_in <= ("00" & LINE6_DC);
        ld_dc <= '1';
        wait until (clk'event and clk = '0');
        ld_dc <= '0';
        pkt_rdy_in <= '1';

        wait until (pkt_in_empty'event and pkt_in_empty = '0');
        wait until (clk'event and clk = '0');
        pkt_rdy_in <= '0';

        wait until (pkt_in_empty'event and pkt_in_empty = '1');
        wait until (clk'event and clk = '0');

        -- Line 7: Load a 43-word HANC packet on line 7.
        anc_in <= ("00" & LINE7_DC);
        ld_dc <= '1';
        wait until (clk'event and clk = '0');
        ld_dc <= '0';
        pkt_rdy_in <= '1';

        wait until (pkt_in_empty'event and pkt_in_empty = '0');
        wait until (clk'event and clk = '0');
        pkt_rdy_in <= '0';

        wait until (pkt_in_empty'event and pkt_in_empty = '1');
        wait until (clk'event and clk = '0');

        -- Line 8: Load a 43-word HANC packet on line 8.
        anc_in <= ("00" & LINE8_DC);
        ld_dc <= '1';
        wait until (clk'event and clk = '0');
        ld_dc <= '0';
        pkt_rdy_in <= '1';

        wait until (pkt_in_empty'event and pkt_in_empty = '0');
        wait until (clk'event and clk = '0');
        pkt_rdy_in <= '0';

        wait until (pkt_in_empty'event and pkt_in_empty = '1');
        wait until (clk'event and clk = '0');

        -- Line 9/10: Attempt to load a 43-word HANC packet on line 9. Because
        -- of the EDH packet, this is one-word too big for line 9 and will be
        -- inserted in the HANC space of line 10.
        anc_in <= ("00" & LINE10_DC);
        ld_dc <= '1';
        wait until (clk'event and clk = '0');
        ld_dc <= '0';
        pkt_rdy_in <= '1';

        wait until (pkt_in_empty'event and pkt_in_empty = '0');
        wait until (clk'event and clk = '0');
        pkt_rdy_in <= '0';

        wait until (pkt_in_empty'event and pkt_in_empty = '1');
        wait until (clk'event and clk = '0');

        -- Line 10/11: Attempt to insert a 43-word ANC packet in either HANC
        -- or VANC space beginning with the VANC space of line 10. Due to
        -- the synchronous-switching keep out areas, this packet should not
        -- load until the VANC space of line 11.
        vanc_pkt <= '1';
        anc_in <= ("00" & LINE11_DC);
        ld_dc <= '1';
        wait until (clk'event and clk = '0');
        ld_dc <= '0';
        pkt_rdy_in <= '1';

        wait until (pkt_in_empty'event and pkt_in_empty = '0');
        wait until (clk'event and clk = '0');
        pkt_rdy_in <= '0';

        wait until (pkt_in_empty'event and pkt_in_empty = '1');
        wait until (clk'event and clk = '0');
        vanc_pkt <= '0';

        -- Line 12: Load a 43-word ANC packet in the HANC space of line 12, but
        -- assert the calc_udw_parity signal.
        calc_udw_parity <= '1';
        anc_in <= ("00" & LINE12_DC);
        ld_dc <= '1';
        wait until (clk'event and clk = '0');
        ld_dc <= '0';
        pkt_rdy_in <= '1';

        wait until (pkt_in_empty'event and pkt_in_empty = '0');
        wait until (clk'event and clk = '0');
        pkt_rdy_in <= '0';

        wait until (pkt_in_empty'event and pkt_in_empty = '1');
        wait until (clk'event and clk = '0');
        calc_udw_parity <= '0';

        -- Reload the DC word with a value of 255. Set the vanc_pkt signal high.
        -- This packet should be too big to fit in the available space in the 
        -- HANC space and should get inserted into the VANC space of line 13.
        vanc_pkt <= '1';
        anc_in <= ("00" & LINE13_DC);
        wait until (trs'event and trs = '0');
        wait until (clk'event and clk = '0');
        ld_dc <= '1';
        wait until (clk'event and clk = '0');
        ld_dc <= '0';
        pkt_rdy_in <= '1';

        wait until (pkt_in_empty'event and pkt_in_empty = '0');
        wait until (clk'event and clk = '0');
        pkt_rdy_in <= '0';

        wait until (pkt_in_empty'event and pkt_in_empty = '1');
        wait until (clk'event and clk = '0');

        wait;
    end process;

    --
    -- This statement stops the simulation when the vcnt value reaches the END_LINE
    -- value the first time after the video_decoder locks. The simulation is stopped
    -- by disabling the clock.
    --
    process
        variable l : line;
        variable success_string :       string (1 to 36) 
                                        := "Test completed with no errors found.";
        variable error_string :         string (1 to 27)
                                        := "Test completed with errors.";
    begin
        wait until (locked'event and locked = '1');
        wait until (vcnt = END_LINE);

        if (error_found) then
            write(l, error_string);
            writeline(output, l);
        else
            write(l, success_string);
            writeline(output, l);
        end if;

        enclk <= '0';
        wait;
    end process;


    --
    -- This code generates expected video output values. Normally, the expected
    -- value is equal to the input video value, delayed appropriately to compensate
    -- for the latency through the processor. However, at certain places, ANC
    -- packets are inserted, so the code below creates expected values to match
    -- those inserted ANC packets.
    --

    -- This first process sets up the values for where the ANC packet should be
    -- inserted, what the length of the packet is, and what the checksum
    -- value should be.
    process(vcnt)
    begin
        case vcnt is
            when "0000000001" =>
                ins_start <= LINE1_INS_START;
                dc_val    <= LINE1_DC;
                cs_val    <= LINE1_CS;
            
            when "0000000010" =>
                ins_start <= LINE2_INS_START;
                dc_val    <= LINE2_DC;
                cs_val    <= LINE2_CS;

            when "0000000100" =>
                ins_start <= LINE4_INS_START;
                dc_val    <= LINE4_DC;
                cs_val    <= LINE4_CS;
            
            when "0000000101" =>
                ins_start <= LINE5_INS_START;
                dc_val    <= LINE5_DC;
                cs_val    <= LINE5_CS;
            
            when "0000000110" =>
                ins_start <= LINE6_INS_START;
                dc_val    <= LINE6_DC;
                cs_val    <= LINE6_CS;
            
            when "0000000111" =>
                ins_start <= LINE7_INS_START;
                dc_val    <= LINE7_DC;
                cs_val    <= LINE7_CS;
            
            when "0000001000" =>
                ins_start <= LINE8_INS_START;
                dc_val    <= LINE8_DC;
                cs_val    <= LINE8_CS;
            
            when "0000001010"  =>
                ins_start <= LINE10_INS_START;
                dc_val    <= LINE10_DC;
                cs_val    <= LINE10_CS;
            
            when "0000001011"  =>
                ins_start <= LINE11_INS_START;
                dc_val    <= LINE11_DC;
                cs_val    <= LINE11_CS;
            
            when "0000001100"  =>
                ins_start <= LINE12_INS_START;
                dc_val    <= LINE12_DC;
                cs_val    <= LINE12_CS;
            
            when "0000001101"  =>
                ins_start <= LINE13_INS_START;
                dc_val    <= LINE13_DC;
                cs_val    <= LINE13_CS;

            when others =>
                ins_start <= (others => '0');
                dc_val    <= (others => '0');
                cs_val    <= (others => '0');

        end case;   
    end process;

    -- This always statement generates the expected video values based on the
    -- ANC packet information from the always statement above.
    process(clk)
    variable temp_ubyte : ubyte_type;
    variable temp_hpos :  std_logic_vector(11 downto 0);
    begin
        if (clk'event and clk = '0') then
            expected_vid <= dly_vid(LATENCY - 1);

            if (locked = '1') then
                
                if (vcnt = vpos_type(TO_UNSIGNED( 1, vpos_type'length)) or
                    vcnt = vpos_type(TO_UNSIGNED( 2, vpos_type'length)) or  
                    vcnt = vpos_type(TO_UNSIGNED( 4, vpos_type'length)) or
                    vcnt = vpos_type(TO_UNSIGNED( 5, vpos_type'length)) or  
                    vcnt = vpos_type(TO_UNSIGNED( 6, vpos_type'length)) or  
                    vcnt = vpos_type(TO_UNSIGNED( 7, vpos_type'length)) or  
                    vcnt = vpos_type(TO_UNSIGNED( 8, vpos_type'length)) or  
                    vcnt = vpos_type(TO_UNSIGNED(10, vpos_type'length)) or  
                    vcnt = vpos_type(TO_UNSIGNED(11, vpos_type'length)) or  
                    vcnt = vpos_type(TO_UNSIGNED(12, vpos_type'length)) or  
                    vcnt = vpos_type(TO_UNSIGNED(13, vpos_type'length)))    
                 then
                    if (hcnt = ins_start) then
                        expected_vid <= ADF0;
                    elsif (hcnt = ins_start + 1 or
                           hcnt = ins_start + 2) then
                        expected_vid <= ADF1;
                    elsif (hcnt = ins_start + DID_WORD) then
                        expected_vid <= pad2_10(INSERT_DID);
                    elsif (hcnt = ins_start + DBN_WORD) then
                        expected_vid <= pad2_10(INSERT_DBN);
                    elsif (hcnt = ins_start + DC_WORD) then
                        expected_vid <= pad2_10(dc_val);
                    elsif (hcnt > ins_start + DC_WORD and
                           hcnt < ins_start + std_logic_vector(dc_val) + 6) then
                        if (vcnt = vpos_type(TO_UNSIGNED(12, vpos_type'length))) then
                            temp_hpos := std_logic_vector(hcnt - ins_start - 6);
                            temp_ubyte := ubyte_type(temp_hpos(7 downto 0));
                            expected_vid <= pad2_10(temp_ubyte);
                        else
                            temp_hpos := std_logic_vector(hcnt - ins_start - 6);
                            expected_vid <= video_type(temp_hpos(9 downto 0) or "1000000000"); 
                        end if;
                    elsif (hcnt = ins_start + std_logic_vector(dc_val) + 6) then
                        expected_vid <= cs_val;
                    end if;
                end if;
            end if;
        end if;
    end process;


    --
    -- Delay the vid_in value by the amount of latency in the anc_edh_processor
    -- module. The delayed video is used as a reference to verify that the video
    -- out of the module is correct.
    --
    process(clk, rst)
    begin
        if (rst = '1') then
            for k in 0 to LATENCY - 1 loop
                dly_vid(k) <= (others => '0');
            end loop;
        elsif (clk'event and clk = '1') then
            for k in 0 to LATENCY - 2 loop
                dly_vid(k+1) <= dly_vid(k);
            end loop;
            dly_vid(0) <= vid_in;
        end if;
    end process;


    --
    -- Compare expected with video out of processor except during the EDH packet.
    -- The EDH packet will not match the input EDH packet value due to EDH
    -- packet processing.
    --
    process(clk)
        variable l  : line;
        variable s1 : string (1 to 17) := "Error: vid_out = ";
        variable s2 : string (1 to 12) := " expected = ";
    begin
        if (clk'event and clk = '1') then
            if (locked = '1' and edh_packet = '0') then
                if (expected_vid /= vid_out) then
                    write(l, s1);
                    hwrite(l, ("00" & vid_out), left, vid_out'length + 2);
                    write(l, s2);
                    hwrite(l, ("00" & expected_vid), left, expected_vid'left + 2);
                    writeline(output, l);
                    error_found <= true;
                end if;
            end if;
        end if;
    end process;


end sim;