📄 test_anc_mux.vhd
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sdid_d: in ubyte_type; -- fourth SDID code to match
del_pkt_d: in std_ulogic; -- packet will be deleted if asserted
-- ANC mux inputs
hanc_pkt: in std_ulogic; -- ANC packet to be sent can be inserted into HANC space
vanc_pkt: in std_ulogic; -- ANC packet to be sent can be inserted into VANC space
pkt_rdy_in: in std_ulogic; -- indicates packet has been loaded into input regs
calc_udw_parity:in std_ulogic; -- indicates that module should calculate parity on UDW
anc_in: in video_type; -- input data bus
ld_did: in std_ulogic; -- load DID register
ld_dbn: in std_ulogic; -- load SDID/DBN register
ld_dc: in std_ulogic; -- load DC register
ld_udw: in std_ulogic; -- loads the UDW RAM
udw_wr_adr: in udwadr_type; -- UDW RAM write address
-- video and decoded video timing outputs
vid_out: out video_type; -- output video stream with EDH packets inserted
std: out vidstd_type; -- video standard code
std_locked: out std_ulogic; -- video standard detector is locked
trs: out std_ulogic; -- asserted during flywheel generated TRS symbol
field: out std_ulogic; -- field indicator
v_blank: out std_ulogic; -- vertical blanking indicator
h_blank: out std_ulogic; -- horizontal blanking indicator
horz_count: out hpos_type; -- horizontal position
vert_count: out vpos_type; -- vertical position
sync_switch: out std_ulogic; -- asserted on lines where synchronous switching is allowed
locked: out std_ulogic; -- asserted when flywheel is synchronized to video
eav_next: out std_ulogic; -- next word is first word of EAV
sav_next: out std_ulogic; -- next word is first word of SAV
xyz_word: out std_ulogic; -- current word is the XYZ word of a TRS
anc_next: out std_ulogic; -- next word is first word of a received ANC packet
edh_next: out std_ulogic; -- next word is first word of a received EDH packet
-- EDH flag outputs
rx_ap_flags: out edh_flgset_type;-- AP error flags received from last EDH packet
rx_ff_flags: out edh_flgset_type;-- FF error flags received from last EDH packet
rx_anc_flags: out edh_flgset_type;-- ANC error flags freceived from last EDH packet
ap_flags: out edh_flgset_type;-- transmitted AP error flags from last field
ff_flags: out edh_flgset_type;-- transmitted FF error flags from last field
anc_flags: out edh_flgset_type;-- transmitted ANC error flags from last field
packet_flags: out edh_pktflg_type;-- error flags related to the received packet processing
errcnt: out edh_errcnt_type;-- errored fields counter
edh_packet: out std_ulogic; -- asserted during all words of a generated EDH packet
-- ANC demux outputs
anc_out: out video_type; -- output packet data
anc_out_valid: out std_ulogic; -- asserted while all words of a matching packet are on anc_out
anc_match: out -- indicates DID/SDID combination matched the current packet
std_ulogic_vector(1 downto 0);
did: out std_ulogic; -- asserted when a DID word from a matching packet is on anc_out
dbn: out std_ulogic; -- asserted when a DBN word from a matching packet is on anc_out
sdid: out std_ulogic; -- asserted when an SDID word from a matching packet is on anc_out
dc: out std_ulogic; -- asserted when a DC word from a matching packet is on anc_out
udw: out std_ulogic; -- asserted when a UDW word from a matching packet is on anc_out
cs: out std_ulogic; -- asserted when a CS word from a matching packet is on anc_out
-- ANC mux outputs
pkt_in_empty: out std_ulogic); -- module is ready for input packet to be loaded
end component;
--
-- pad2_10 function
--
-- This function takes an 8-bit value, computes a parity bit, then creates a
-- 10-bit word with the complement of the parity bit in bit 9 and the parity
-- bit in bit 8, followed by the original 8-bit value.
--
function pad2_10(d: ubyte_type) return video_type is
variable parity : std_ulogic;
begin
parity := d(7) xor d(6) xor d(5) xor d(4) xor d(3) xor d(2) xor d(1) xor d(0);
return(not parity & parity & d);
end pad2_10;
begin
--
-- Instantiate the ANC/EDH processor module
--
U1 : anc_edh_processor
port map (
clk => clk,
ce => rx_ce,
rst => rst,
vid_in => vid_in,
reacquire => GND,
en_sync_switch => VCC,
en_trs_blank => VCC,
anc_idh_local => anc_idh_local,
anc_ues_local => anc_ues_local,
ap_idh_local => ap_idh_local,
ff_idh_local => ff_idh_local,
errcnt_flg_en => errcnt_flg_en,
clr_errcnt => GND,
receive_mode => VCC,
en_a => GND,
did_a => GND8,
sdid_a => GND8,
del_pkt_a => GND,
en_b => GND,
did_b => GND8,
sdid_b => GND8,
del_pkt_b => GND,
en_c => GND,
did_c => GND8,
sdid_c => GND8,
del_pkt_c => GND,
en_d => GND,
did_d => GND8,
sdid_d => GND8,
del_pkt_d => GND,
hanc_pkt => hanc_pkt,
vanc_pkt => vanc_pkt,
pkt_rdy_in => pkt_rdy_in,
calc_udw_parity => calc_udw_parity,
anc_in => anc_in,
ld_did => ld_did,
ld_dbn => ld_dbn,
ld_dc => ld_dc,
ld_udw => ld_udw,
udw_wr_adr => udw_wr_adr,
vid_out => vid_out,
std => std,
std_locked => std_locked,
trs => trs,
field => f,
v_blank => v,
h_blank => h,
horz_count => hcnt,
vert_count => vcnt,
sync_switch => sync_switch,
locked => locked,
eav_next => eav_next,
sav_next => sav_next,
xyz_word => xyz_word,
anc_next => anc_next,
edh_next => edh_next,
rx_ap_flags => rx_ap_flags,
rx_ff_flags => rx_ff_flags,
rx_anc_flags => rx_anc_flags,
ap_flags => ap_flags,
ff_flags => ff_flags,
anc_flags => anc_flags,
packet_flags => packet_flags,
errcnt => errcnt,
edh_packet => edh_packet,
anc_out => open,
anc_out_valid => open,
anc_match => open,
did => open,
dbn => open,
sdid => open,
dc => open,
udw => open,
cs => open,
pkt_in_empty => pkt_in_empty);
edh_format_err <= packet_flags(3);
edh_chksum_err <= packet_flags(2);
edh_parity_err <= packet_flags(1);
edh_missing <= packet_flags(0);
--
-- Read in one frame of NTSC video into memory array
--
process
file infile: TEXT open read_mode is "C:/work/XAPP299/sim/one_frame.txt";
variable buf: line;
variable data: std_logic_vector(11 downto 0);
variable words: integer := 0;
variable good: boolean;
begin
while not (endfile(infile)) loop
readline(infile, buf); -- read a line from file into buffer
for i in 0 to 15 loop -- there are 16 words per line in the file
exit when words = MAX_MEM; -- last line doesn't contain 16 words so put an early escape mechanism here
hread(buf, data, good); -- read one word from the buffer
assert good -- make sure the read was OK
report "Text I/O read error"
severity failure;
memory(words) := video_type(data(9 downto 0)); -- write word to the memory array
words := words + 1;
end loop;
end loop;
wait;
end process;
--
-- Generate a clock signal at 27 MHz.
--
clk <= enclk and not clk after 18.5 ns;
rx_ce <= '1';
--
-- Assert the reset signal for the first few clock cycles
--
process
begin
for count in 1 to 5 loop
wait until clk'event and clk = '0';
end loop;
rst <= '0';
wait;
end process;
--
-- This code generates the index into the memory array and the frame counter.
-- The index begins at a negative number. When the index is negative, no video
-- is generated. A few cycles with no video are used to make sure the modules
-- come out of reset before the test set is sent. When the index reaches the
-- maximum size of the memory array, it is reset to zero and the frame counter
-- is incremented.
--
process(clk, rst)
begin
if (rst = '1') then
i <= -5;
frames <= 0;
elsif (clk'event and clk = '1') then
if (i = MAX_MEM - 1 and frames < 8) then
i <= 0;
frames <= frames + 1;
else
i <= i + 1;
end if;
end if;
end process;
--
-- Whenever the memory index changes, look up a new video data value from the
-- memory array and assign that value to vid_in.
--
process(i)
begin
if (i < 0 or i >= MAX_MEM or frames > 7) then
vid_in <= (others => '0');
else
vid_in <= memory(i);
end if;
end process;
--
-- The following code scripts the insertion of ANC packets into the
-- anc_edh_processor module.
--
process
begin
pkt_rdy_in <= '0';
hanc_pkt <= '1';
vanc_pkt <= '0';
ld_did <= '0';
ld_dbn <= '0';
ld_udw <= '0';
ld_dc <= '0';
calc_udw_parity <= '0';
wait until (rst'event and rst = '0');
for j in 1 to 5 loop
wait until (clk'event and clk = '0');
end loop;
-- Load the UDW RAM with data.
for j in 0 to 255 loop
udw_wr_adr <= udwadr_type(TO_UNSIGNED(j, udw_wr_adr'length));
anc_in <= video_type("1000000000" + std_logic_vector(TO_UNSIGNED(j, video_type'length)));
ld_udw <= '1';
wait until (clk'event and clk = '0');
end loop;
ld_udw <= '0';
-- Write the DID value
anc_in <= ("00" & INSERT_DID);
ld_did <= '1';
wait until (clk'event and clk = '0');
-- Write the DBN value
ld_did <= '0';
anc_in <= ("00" & INSERT_DBN);
ld_dbn <= '1';
wait until (clk'event and clk = '0');
-- Line1: Set the DC value for the first packet to 206, exactly the
-- amount of available HANC space in Line 1.
ld_dbn <= '0';
anc_in <= ("00" & LINE1_DC);
ld_dc <= '1';
wait until (clk'event and clk = '0');
ld_dc <= '0';
-- Now wait for the video decoder to lock, then wait for vcnt == 1.
wait until (locked'event and locked = '1');
wait until (vcnt = 1);
wait until (clk'event and clk = '0');
pkt_rdy_in <= '1';
wait until (pkt_in_empty'event and pkt_in_empty = '0');
wait until (clk'event and clk = '0');
pkt_rdy_in <= '0';
wait until (pkt_in_empty'event and pkt_in_empty = '1');
wait until (clk'event and clk = '0');
-- Line 2: Insert a HANC packet of length 9.
anc_in <= ("00" & LINE2_DC);
ld_dc <= '1';
wait until (clk'event and clk = '0');
ld_dc <= '0';
pkt_rdy_in <= '1';
wait until (pkt_in_empty'event and pkt_in_empty = '0');
wait until (clk'event and clk = '0');
pkt_rdy_in <= '0';
wait until (pkt_in_empty'event and pkt_in_empty = '1');
wait until (clk'event and clk = '0');
-- Line 3/4: Attempt to insert a HANC packet of length 43. This is
-- one word too large for the available HANC space of line 3 and will
-- be inserted in line 4.
anc_in <= ("00" & LINE4_DC);
ld_dc <= '1';
wait until (clk'event and clk = '0');
ld_dc <= '0';
pkt_rdy_in <= '1';
wait until (pkt_in_empty'event and pkt_in_empty = '0');
wait until (clk'event and clk = '0');
pkt_rdy_in <= '0';
wait until (pkt_in_empty'event and pkt_in_empty = '1');
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