📄 test_anc_mux.vhd
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--------------------------------------------------------------------------------
-- test_anc_mux.vhd
--
-- Testbench for ANC packet MUX function of the anc_edh_processor module
--
--
--
-- Author: John F. Snow
-- Staff Applications Engineer
--
-- Video Applications
-- Advanced Products Group
-- Xilinx, Inc.
--
-- Copyright (c) 2002 Xilinx, Inc.
-- All rights reserved
--
-- Date: May 8, 2002
--
-- RESTRICTED RIGHTS LEGEND
--
-- This software has not been published by the author, and
-- has been disclosed to others for the purpose of enhancing
-- and promoting design productivity in Xilinx products.
--
-- Therefore use, duplication or disclosure, now and in the
-- future should give consideration to the productivity
-- enhancements afforded the user of this code by the author's
-- efforts. Thank you for using our products !
--
-- Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY
-- WHATSOEVER AND XILINX SPECIFICALLY DISCLAIMS ANY
-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
-- A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
--
-- Revision:
-- May 8, 2002 Translated from Verilog
--
--
--------------------------------------------------------------------------------
-- !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
-- IMPORTANT NOTE:
--
-- This testbench uses shared variables and VHDL '93 file I/O syntax. It must
-- be compiled by a VHDL '93 compliant compiler. In ModelSim, the default is
-- to generated errors on VHDL '93 specific syntax and the -93 flag must be
-- used.
--!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
--
-- This testbench tests the ANC packet insert function of the anc_edh_processor
-- module.
--
-- The testbench reads a full frame of video data from the one_frame.txt file
-- into a memory array. This frame of video is fed into the anc_edh_processor
-- repeatedly until the testbench terminates.
--
-- The testbench begins by loading information about the ANC packet to be
-- inserted in the video stream. A DID value of h'c5 and a DBN value of 0 are
-- used. The data count value (DC) varies from packet to packet, depending on
-- the specific test situation. The UDW words loaded into ANC packet generator
-- begin at zero for the first word and increment by one for each word up to 255.
--
-- To test the ANC packet insert function, the testbench first waits for the
-- anc_edh_processor module to lock to the video stream, as indicated by the
-- assertion of the locked output. Once lock is achieved, the testbench waits
-- for vertical line number 1. The first few video lines in one_frame.txt have
-- extra ANC packets inserted in the HANC space to facilitate testing of the ANC
-- packet insertion function. Once line 1 begins, the testbench loads a DC value
-- and asserts the pkt_rdy_in signal repeatedly to cause an ANC packet to be
-- inserted several times over a period of 13 video lines.
--
-- Line 1: In one_frame.txt, the HANC space of line 1 contains a 55-word long
-- ANC packet followed by an end_marker packet. Including the space occupied by
-- the end_marker packet, there is 213 words of space available in the HANC
-- space. The testbench attempts to insert a new ANC packet that is exactly 213
-- words long.
--
-- Line 2: In one_frame.txt, the HANC space of line 2 contains several ANC
-- packets followed by an end_marker packet. Including the space occupied by the
-- end_marker packet, there are 10 words of free space. The testbench attempts
-- to insert an ANC packet that is 9 words long.
--
-- Line 3/4: In one_frame.txt, there are 42 free words available in the HANC
-- space of line 3 and 43 free words in the HANC space of line 4. The testbench
-- attempts to insert an ANC packet that is 43 words long. This module should
-- not insert this packet in line 3 due to lack of space, but it should insert
-- it in line 4.
--
-- Line 5: In one_frame.txt, the HANC space begins with a 43-word long ANC
-- packet. There is no end_marker packet. There are 225 free words in the HANC
-- space. The testbench attempts to insert an ANC packet that is exactly 225
-- words long.
--
-- Line 6: In one_frame.txt, the HANC space begins with a 43-word long ANC
-- packet and there is no end_marker packet. The testbench attempts to insert an
-- ANC packet that is 23 words long.
--
-- Line 7: In one_frame.txt, the HANC space of line 7 begins with a conforming
-- 43-word long ANC packet followed by a start_marker packet, 175 words of
-- non-conforming ANC data, then an end_marker packet. Including the end_marker
-- packet, there are 43 words of available HANC space. The testbench attempts to
-- insert an ANC packet that is 43 words long.
--
-- Line 8: In one_frame.txt, the HANC space of line 8 contains one ANC packet
-- that is 43 words long with no end_marker packet. The testbench attempts to
-- insert a 43-word long ANC packet.
--
-- Line 9/10: In one_frame.txt, the HANC space of line 9 contains a 55-word long
-- ANC packet, a start_marker packet, 141 words of non-conforming ANC data, an
-- end_marker packet, 35 free words, and the EDH packet. Including the
-- end_marker packet, there are 42 words of free space. The testbench attempts
-- to insert an ANC packet that is 43 words long. This shouldn't fit if the
-- space-available calculation correctly takes into consideration the EDH
-- packet. Instead, the ANC packet should be inserted on line 10 which an
-- entirely empty ANC space in the one_frame.txt file.
--
-- Line 10/11: The VANC space of line 10 and the HANC space of line 11 are keep-
-- out areas due to synchronous switching. After the ANC packet is inserted in
-- the HANC space of line 10, the testbench immediately sets up an ANC packet
-- that can be inserted in either the HANC or VANC space. The module should not
-- insert this packet until the VANC space of line 11 due to the keep out areas.
--
-- Line 12: The testbench simply tries to insert a HANC packet that is 43 words
-- long. This should easily fit in the HANC space of line 12. In this case, the
-- calc_udw_parity input signal is asserted to cause the module to generate
-- parity bits for the UDW data.
--
-- Line 13: The testbench attempts to insert a 262-word long ANC packet and
-- indicates that it can go in either the HANC or VANC space. This packet is too
-- long to fit in the available HANC space of line 13 and should be inserted in
-- the VANC space.
--
library ieee;
use std.textio.all;
use ieee.std_logic_textio.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use work.anc_edh_pkg.all;
entity test_anc_mux is
constant MAX_MEM : integer := 900900; -- Size of memory needed to hold 1 frame NTSC
type mem_type is array (MAX_MEM - 1 downto 0) of video_type;
end;
architecture sim of test_anc_mux is
shared variable memory : mem_type; -- Memory array holding test video
--------------------------------------------------------------------------------
-- Constant definitions
--
constant FIRST_EDH : integer := 13977; -- Position in memory of start of 1st EDH packet
constant SECOND_EDH : integer := 465285; -- Position in memory of start of 2nd EDH packet
-- These constants specify the positions of some words in the ANC packet.
constant DID_WORD : integer := 3;
constant DBN_WORD : integer := 4;
constant DC_WORD : integer := 5;
-- These constants define the values of certain words in inserted ANC packets.
constant ADF0 : video_type := "0000000000";
constant ADF1 : video_type := "1111111111";
constant INSERT_DID : ubyte_type := ubyte_type(TO_UNSIGNED(16#c5#, ubyte_type'length));
constant INSERT_DBN : ubyte_type := "00000000";
-- These constants give the starting positions of inserted ANC packets along
-- with the DC value indicating the length of the ANC packet and the resulting
-- checksum word.
constant LINE1_INS_START : hpos_type := hpos_type(TO_UNSIGNED(1499, hpos_type'length));
constant LINE1_DC : ubyte_type := ubyte_type(TO_UNSIGNED(206, ubyte_type'length));
constant LINE1_CS : video_type := video_type(TO_UNSIGNED(16#10e#, video_type'length));
constant LINE2_INS_START : hpos_type := hpos_type(TO_UNSIGNED(1702, hpos_type'length));
constant LINE2_DC : ubyte_type := ubyte_type(TO_UNSIGNED(2, ubyte_type'length));
constant LINE2_CS : video_type := video_type(TO_UNSIGNED(16#1c8#, video_type'length));
constant LINE4_INS_START : hpos_type := hpos_type(TO_UNSIGNED(1669, hpos_type'length));
constant LINE4_DC : ubyte_type := ubyte_type(TO_UNSIGNED(36, ubyte_type'length));
constant LINE4_CS : video_type := video_type(TO_UNSIGNED(16#15f#, video_type'length));
constant LINE5_INS_START : hpos_type := hpos_type(TO_UNSIGNED(1487, hpos_type'length));
constant LINE5_DC : ubyte_type := ubyte_type(TO_UNSIGNED(218, ubyte_type'length));
constant LINE5_CS : video_type := video_type(TO_UNSIGNED(16#104#, video_type'length));
constant LINE6_INS_START : hpos_type := hpos_type(TO_UNSIGNED(1487, hpos_type'length));
constant LINE6_DC : ubyte_type := ubyte_type(TO_UNSIGNED(16, ubyte_type'length));
constant LINE6_CS : video_type := video_type(TO_UNSIGNED(16#24d#, video_type'length));
constant LINE7_INS_START : hpos_type := hpos_type(TO_UNSIGNED(1669, hpos_type'length));
constant LINE7_DC : ubyte_type := ubyte_type(TO_UNSIGNED(36, ubyte_type'length));
constant LINE7_CS : video_type := video_type(TO_UNSIGNED(16#15f#, video_type'length));
constant LINE8_INS_START : hpos_type := hpos_type(TO_UNSIGNED(1487, hpos_type'length));
constant LINE8_DC : ubyte_type := ubyte_type(TO_UNSIGNED(36, ubyte_type'length));
constant LINE8_CS : video_type := video_type(TO_UNSIGNED(16#15f#, video_type'length));
constant LINE10_INS_START: hpos_type := hpos_type(TO_UNSIGNED(1444, hpos_type'length));
constant LINE10_DC : ubyte_type := ubyte_type(TO_UNSIGNED(36, ubyte_type'length));
constant LINE10_CS : video_type := video_type(TO_UNSIGNED(16#15f#, video_type'length));
constant LINE11_INS_START: hpos_type := hpos_type(TO_UNSIGNED(0, hpos_type'length));
constant LINE11_DC : ubyte_type := ubyte_type(TO_UNSIGNED(36, ubyte_type'length));
constant LINE11_CS : video_type := video_type(TO_UNSIGNED(16#15f#, video_type'length));
constant LINE12_INS_START: hpos_type := hpos_type(TO_UNSIGNED(1487, hpos_type'length));
constant LINE12_DC : ubyte_type := ubyte_type(TO_UNSIGNED(36, ubyte_type'length));
constant LINE12_CS : video_type := video_type(TO_UNSIGNED(16#15f#, video_type'length));
constant LINE13_INS_START: hpos_type := hpos_type(TO_UNSIGNED(0, hpos_type'length));
constant LINE13_DC : ubyte_type := ubyte_type(TO_UNSIGNED(255, ubyte_type'length));
constant LINE13_CS : video_type := video_type(TO_UNSIGNED(16#245#, video_type'length));
constant END_LINE : vpos_type := vpos_type(TO_UNSIGNED(14, vpos_type'length));
--
-- This constant specifies the number of cycles of clock latency through the
-- anc_edh_processor, including video decoder latency.
--
constant LATENCY : integer := 10;
--------------------------------------------------------------------------------
-- Signal definitions
--
--
-- These signals connect to the modules in the test bench
--
signal clk : std_ulogic := '0'; -- clock signal
signal enclk : std_ulogic := '1'; -- clock enable signal
signal rst : std_ulogic := '1'; -- reset signal
signal vid_in : video_type; -- output of memory array
signal std_locked : std_ulogic; -- video standard dectector locked
signal std: vidstd_type; -- video standard code
signal trs: std_ulogic; -- video decoder TRS
signal vid_out: video_type; -- video output of edh_processor
signal f: std_ulogic; -- field indicator
signal v: std_ulogic; -- vertical blanking indicator
signal h: std_ulogic; -- horizontal blanking indicator
signal hcnt: hpos_type; -- horizontal counter
signal vcnt: vpos_type; -- vertical counter
signal sync_switch: std_ulogic; -- sync switching line
signal locked: std_ulogic; -- flywheel locked
signal eav_next: std_ulogic; -- EAV is next
signal sav_next: std_ulogic; -- SAV is next
signal xyz_word: std_ulogic; -- current word is XYZ word
signal anc_next: std_ulogic; -- ANC is next
signal edh_next: std_ulogic; -- EDH is next
signal rx_ce: std_ulogic; -- clock enable
signal edh_packet: std_ulogic; -- edh processor EDH packet indicator
signal edh_missing: std_ulogic; -- edh packet was missing
signal edh_parity_err: std_ulogic; -- edh packet parity error
signal edh_chksum_err: std_ulogic; -- edh packet checksum error
signal edh_format_err: std_ulogic; -- edh packet format error
signal rx_ap_flags: edh_flgset_type; -- received edh packet AP flags
signal rx_ff_flags: edh_flgset_type; -- received edh packet FF flags
signal rx_anc_flags: edh_flgset_type; -- recevied edh packet ANC flags
signal ap_flags: edh_flgset_type; -- transmitted edh packet AP flags
signal ff_flags: edh_flgset_type; -- transmitted edh packet FF flags
signal anc_flags: edh_flgset_type; -- transmitted edh packet ANC flags
signal errcnt: edh_errcnt_type; -- count of fields containing EDH errors
signal anc_idh_local: std_ulogic := '0'; -- controls the ANC IDH local input to EDH proc
signal anc_ues_local: std_ulogic := '0'; -- controls the ANC UES local input to EDH proc
signal ap_idh_local: std_ulogic := '0'; -- controls the AP IDH local input to EDH proc
signal ff_idh_local: std_ulogic := '0'; -- controls the FF IDH local input to EDH proc
signal errcnt_flg_en: edh_allflg_type -- controls the error count flag enables
:= "1111111111111111";
signal hanc_pkt: std_ulogic; -- asserted if ANC packet is to be inserted in HANC space
signal vanc_pkt: std_ulogic; -- asserted if ANC packet is to be inserted in VACN space
signal pkt_rdy_in: std_ulogic; -- asserted when ANC packet is ready to send
signal calc_udw_parity: std_ulogic; -- causes module to compute parity for UDW words
signal anc_in: video_type; -- ANC packet input data bus
signal ld_did: std_ulogic; -- Loads DID word of ANC packet
signal ld_dbn: std_ulogic; -- Loads DBN/SDID word of ANC packet
signal ld_dc: std_ulogic; -- Loads the DC word of ANC packet
signal ld_udw: std_ulogic; -- Loads the UDW words of ANC packet
signal udw_wr_adr: udwadr_type; -- UDW RAM write address
signal pkt_in_empty: std_ulogic; -- status output of ANC MUX
signal packet_flags : edh_pktflg_type; -- vector containing the packet error flags listed below
--
-- These signals control the testbench
--
type dly_video_type is array (LATENCY-1 downto 0) of video_type;
signal i: integer; -- index into memory array
signal frames: integer; -- counts number of frames during test
signal error_found: boolean := false; -- asserted when a simulation error is detected
signal expected_vid: video_type; -- expected video value
signal dly_vid: dly_video_type; -- delays vid_in for output comparison
signal ins_start: hpos_type; -- ANC packet insertion starting position
signal dc_val: ubyte_type; -- inserted ANC packet DC value
signal cs_val: video_type; -- inserted ANC packet CS value
signal VCC : std_ulogic := '1';
signal GND : std_ulogic := '0';
signal GND8 : ubyte_type := "00000000";
component anc_edh_processor
port (
clk: in std_ulogic; -- clock input
ce: in std_ulogic; -- clock enable
rst: in std_ulogic; -- async reset input
-- video decoder inputs
vid_in: in video_type; -- input video
reacquire: in std_ulogic; -- forces autodetect to reacquire the video standard
en_sync_switch: in std_ulogic; -- enables synchronous switching
en_trs_blank: in std_ulogic; -- enables TRS blanking when asserted
-- EDH flag inputs
anc_idh_local: in std_ulogic; -- ANC IDH flag input
anc_ues_local: in std_ulogic; -- ANC UES flag input
ap_idh_local: in std_ulogic; -- AP IDH flag input
ff_idh_local: in std_ulogic; -- FF IDH flag input
errcnt_flg_en: in edh_allflg_type;-- selects which error flags increment the error counter
clr_errcnt: in std_ulogic; -- clears the error counter
receive_mode: in std_ulogic; -- 1 enables receiver, 0 for generate only
-- ANC demux inputs
en_a: in std_ulogic; -- enable for DID A decoder
did_a: in ubyte_type; -- first DID code to match
sdid_a: in ubyte_type; -- first SDID code to match
del_pkt_a: in std_ulogic; -- packet will be deleted if asserted
en_b: in std_ulogic; -- enable for DID B decoder
did_b: in ubyte_type; -- second DID code to match
sdid_b: in ubyte_type; -- second SDID code to match
del_pkt_b: in std_ulogic; -- packet will be deleted if asserted
en_c: in std_ulogic; -- enable for DID C decoder
did_c: in ubyte_type; -- third DID code to match
sdid_c: in ubyte_type; -- third SDID code to match
del_pkt_c: in std_ulogic; -- packet will be deleted if asserted
en_d: in std_ulogic; -- enable for DID D decoder
did_d: in ubyte_type; -- fourth DID code to match
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