anc_extract.vhd

XAPP299 version 1.0 reference design files

            when S_ADF3 =>
                if (match = '1') then
                    set_do_valid <= '1';
                else
                    set_do_valid <= '0';
                end if;
                clr_checksum <= '1';
                ld_match_code <= '1';

            when S_DID =>
                did <= '1';
                if (pkt_delete = '1') then
                    do_delete <= '1';
                end if;

            when S_SDID =>
                if (pkt_type = '1') then
                    dbn <= '1';
                else
                    sdid <= '1';
                end if;

            when S_DC =>
                dc <= '1';
                ld_udw_cntr <= '1';

            when S_UDW =>
                udw <= '1';

            when S_CS =>
                cs <= '1';
                clr_do_valid <= '1';
                output_checksum <= '1';

            when others =>
        end case;
    end process;

    --
    -- pkt_delete register
    --
    -- This register has a MUX at the input. This MUX selects the appropriate
    -- del_pkt_[a:d] input depending on which DID/SDID pair matched the packet.
    -- The register implements a one clock delay so that pkt_delete is valid when
    -- the state machine needs it.
    --
    process(clk,rst)
    begin
        if (rst = '1') then
            pkt_delete <= '0';
        elsif (clk'event and clk = '1') then
            if (ce = '1') then
                case encoded_match is
                    when "00" =>   pkt_delete <= del_pkt_a;
                    when "01" =>   pkt_delete <= del_pkt_b;
                    when "10" =>   pkt_delete <= del_pkt_c;
                    when "11" =>   pkt_delete <= del_pkt_d;
                    when others => pkt_delete <= '0'; 
                end case;
            end if;
        end if;
    end process;

    --
    -- video delay registers
    --
    -- The input video stream is delayed through a pipeline of three registers so
    -- that the module has time to examine the DID and SDID words for a match 
    -- before acting on the packet.
    --
    process(clk,rst)
    begin
        if (rst = '1') then
            vid_in_reg <= (others => '0');
            vid_dly_1 <= (others => '0');
            vid_dly_2 <= (others => '0');
        elsif (clk'event and clk = '1') then
            if (ce = '1') then
                vid_in_reg <= vid_in;
                vid_dly_1 <= vid_in_reg;
                vid_dly_2 <= vid_dly_1;
            end if;
        end if;
    end process;
            
    --
    -- video output MUX
    --
    -- The output video stream is normally equal to the contents of the vid_dly_2
    -- register. However, if do_delete is asserted, the deletion code is output
    -- in place of the DID word. If the output_checksum signal is asserted, then
    -- the contents of the checksum generator is output in place of the checksum
    -- in the packet. Note that the MUX is actually implemented as two cascaded
    -- MUXes because the checksum generator needs the intermediate value called
    -- vid_mux.
    --

    vid_mux <= DEL_DID when do_delete = '1' else vid_dly_2;

    vid_out <= ((not checksum(8)) & checksum) when output_checksum = '1' 
               else vid_mux;
     
    --
    -- UDW counter
    --
    -- The UDW counter counts the number of user data words in the packet so that
    -- the FSM knows when all of the user data words in the packet have been
    -- processed. A MUX selects between the DC value from the input video stream
    -- or the contents of the UDW counter. The output of the MUX is decrement by
    -- one before being loaded into the UDW counter. The output of the MUX is also
    -- tested to see if it is equal to zero and udw_cntr_eq_0 is asserted if so.
    -- Because the FSM needs to test both the DC value and the UDW counter for zero
    -- this design uses only one comparator to do both tests.
    --
    udw_cntr_mux <= vid_dly_2(7 downto 0) when ld_udw_cntr = '1' else udw_cntr;

    udw_cntr_eq_0 <= '1' when udw_cntr_mux = UBYTE_ZERO else '0';

    process(clk, rst)
    begin
        if (rst = '1') then
            udw_cntr <= (others => '0');
        elsif (clk'event and clk = '1') then
            if (ce = '1') then
                udw_cntr <= std_ulogic_vector(std_logic_vector(udw_cntr_mux) - 1);
            end if;
        end if;
    end process;

    -- 
    -- anc_next_dly register
    --
    -- This register delays the anc_next input signal by three clock cycles -- 
    -- matching the pipeline delay that the module implements on the video path.
    --
    process(clk,rst)
    begin
        if (rst = '1') then
            anc_next_dly <= (others => '0');
        elsif (clk'event and clk = '1') then
            if (ce = '1') then
                anc_next_dly <= (anc_next_dly(1 downto 0) & anc_next);
            end if;
        end if;
    end process;

    --
    -- data_out_valid logic
    --
    -- The data_out_valid signal is controlled by the set_do_valid and clr_do_valid
    -- signals from the FSM. This signal becomes asserted when the DID word is
    -- present on the data_out port and stays asserted through the clock cycle when
    -- the checksum word is present on the data_out port.
    --
    process(clk,rst)
    begin
        if (rst = '1') then
            data_out_valid <= '0';
        elsif (clk'event and clk = '1') then
            if (ce = '1') then
                if (set_do_valid = '1') then
                    data_out_valid <= '1';
                elsif (clr_do_valid = '1') then
                    data_out_valid <= '0';
                end if;
            end if;
        end if;
    end process;

    --
    -- The data_out port carries the demuxed packet information. It is simply
    -- set to the value of the vid_dly_2 register. The data_out_valid signal
    -- can be used to determine when valid information is present on this port.
    --
    data_out <= vid_dly_2;

    --
    -- checksum generator
    --
    -- This logic generates a 9-bit checksum for the ANC packet. A new checksum
    -- is generated in case the packet was marked for deletion by the module by
    -- changing the DID value. This causes the checksum to change.
    --
    process(clk, rst)
    begin
        if (rst = '1') then
            checksum <= (others => '0');
        elsif (clk'event and clk = '1') then
            if (ce = '1') then
                if (clr_checksum = '1') then
                    checksum <= (others => '0');
                else
                    checksum <= std_ulogic_vector(std_logic_vector(checksum) +
                                                  std_logic_vector(vid_mux(8 downto 0)));
                end if;
            end if;
        end if;
    end process;

    -----------------------------------------------------------------------------
    -- DID/SDID match logic
    --
    -- This logic first compares the DID word with the four input DID values. Next
    -- The SDID word is compared with the four input SDID values but this comparison
    -- is only used for type 2 packets (pkt_type = 0). If the DID/SDID pair matches
    -- one of the four input pairs, then the match signal is asserted, and a 2-bit 
    -- code indicating which pair matched is loaded into the match_code register.
    --

    --
    -- This code generates the did_8_bit_d and did_8_bit signals. The did_8_bit_d
    -- signal is asserted when the vid_in_reg value indicates an 8-bit DID value.
    -- This signal is delayed by one clock cycle to generated the did_8_bit signal.
    -- The eight_bit signal is a combination of these two signals. It is equal to
    -- did_8_bit_d when the DID word is in the vid_in_reg, otherwise it is equal
    -- to the did_8_bit signal.
    --
    did_8_bit_d <= not vid_in_reg(7) and not vid_in_reg(6) and not vid_in_reg(5) and
                   not vid_in_reg(4) and (vid_in_reg(3) or vid_in_reg(2));

    process(clk,rst)
    begin
        if (rst = '1') then
            did_8_bit <= '0';
        elsif (clk'event and clk = '1') then
            if (ce = '1') then
                did_8_bit <= did_8_bit_d;
            end if;
        end if;
    end process;

    eight_bit <= did_8_bit_d when check_did = '1' else did_8_bit;

    --
    -- The pkt_type signal is derived from the DID word in the input video stream.
    -- It is asserted for type 1 ANC packets and negated for type 2 ANC packets.
    --
    process(clk, rst)
    begin
        if (rst = '1') then
            pkt_type <= '0';
        elsif (clk'event and clk = '1') then
            if (ld_pkt_type = '1') then
                pkt_type <= vid_in_reg(7);
            end if;
        end if;
    end process;

    --
    -- The following MUXes select between the the DID and SDID values for each pair
    -- so that the proper value is fed to the comparators to be tested against the
    -- DID and SDID words in the packet.
    --
    mux_a <= did_a when check_did = '1' else sdid_a;
    mux_b <= did_b when check_did = '1' else sdid_b;
    mux_c <= did_c when check_did = '1' else sdid_c;
    mux_d <= did_d when check_did = '1' else sdid_d;

    --
    -- These equations are for 8-bit conditioning. The outputs of the DID/SDID\
    -- MUXes are converted to 8-bit values if the eight_bit signal is asserted.
    -- Likewise, the DID and SDID words from the input video stream are converted
    -- to 8-bit values if eight_bit is asserted. 
    a_x <=  (mux_a(7 downto 2) & (mux_a(1) and not eight_bit) & 
             (mux_a(0) and not eight_bit));
    b_x <=  (mux_b(7 downto 2) & (mux_b(1) and not eight_bit) & 
             (mux_b(0) and not eight_bit));
    c_x <=  (mux_c(7 downto 2) & (mux_c(1) and not eight_bit) & 
             (mux_c(0) and not eight_bit));
    d_x <=  (mux_d(7 downto 2) & (mux_d(1) and not eight_bit) & 
             (mux_d(0) and not eight_bit));
    in_x <= (vid_in_reg(7 downto 2) & (vid_in_reg(1) and not eight_bit) & 
             (vid_in_reg(0) and not eight_bit));
    --
    -- These MUXes first compare the DID values with the contents of the vid_in_reg
    -- and then, on the next clock cycle, they compare the SDID values with the
    -- contents of the vid_in_reg.
    --
    cmp_a <= '1' when en_a = '1' and (a_x = in_x) else '0';
    cmp_b <= '1' when en_b = '1' and (b_x = in_x) else '0';
    cmp_c <= '1' when en_c = '1' and (c_x = in_x) else '0';
    cmp_d <= '1' when en_d = '1' and (d_x = in_x) else '0';

    --
    -- The did_match register holds the outputs of the comparators after the DID
    -- comparison is done.
    --
    process(clk, rst)
    begin
        if (rst = '1') then
            did_match <= (others => '0');
        elsif (clk'event and clk = '1') then
            if (ce = '1') then
                did_match <= (cmp_d & cmp_c & cmp_b & cmp_a);
            end if;
        end if;
    end process;

    --
    -- This statement essentially ORs the pkt_type bit with the output of the
    -- comparators when the SDID comparison is done. This insures that for type 1
    -- packets the results of the SDID word comparison are forced to be true. For
    -- type 1 packets, there is no SDID word and the comparison is invalid.
    --
    sdid_match <= (others => '1') when pkt_type = '1' 
                  else (cmp_d & cmp_c & cmp_b & cmp_a);

    --
    -- If both the DID word and the SDID word match, then the corresponding matches
    -- bit is asserted.
    --
    matches <= sdid_match and did_match;

    --
    -- The match signal is asserted if any of the DID/SDID pairs were successfully
    -- matched with the packet. It is generated by ORing the matches vector.
    --
    match <= matches(3) or matches(2) or matches(1) or matches(0);

    --
    -- This code generates the encoded_match signal. This is a priority encoded
    -- value derived from the matches vector.
    --
    process(matches)
    begin
        if (matches(0) = '1') then
            encoded_match <= "00";
        elsif (matches(1) = '1') then
            encoded_match <= "01";
        elsif (matches(2) = '1') then
            encoded_match <= "10";
        elsif (matches(3) = '1') then
            encoded_match <= "11";
        else
            encoded_match <= "00";
        end if;
    end process;

    --
    -- The match_code register holds the encoded_match value for the entire duration
    -- that the packet is being output by the module.
    --
    process(clk,rst)
    begin
        if (rst = '1') then
            match_code <= (others => '0');
        elsif (clk'event and clk = '1') then
            if (ce = '1' and ld_match_code = '1') then
                match_code <= encoded_match;
            end if;
        end if;
    end process;

end synth;