anc_extract.vhd

XAPP299 version 1.0 reference design files

--------------------------------------------------------------------------------
-- anc_extract.vhd
--
-- SDI ANC packet demultiplexor and packet deletion module
--
--
--
--                  Author: John F. Snow
--                  Staff Applications Engineer
--
--                  Video Applications
--                  Advanced Products Group
--                  Xilinx, Inc.
--
--                  Copyright (c) 2002 Xilinx, Inc.
--                  All rights reserved
--
--                  Date:   May 8, 2002
--
--                  RESTRICTED RIGHTS LEGEND
--
--      This software has not been published by the author, and 
--      has been disclosed to others for the purpose of enhancing 
--      and promoting design productivity in Xilinx products.
--
--      Therefore use, duplication or disclosure, now and in the 
--      future should give consideration to the productivity 
--      enhancements afforded the user of this code by the author's 
--      efforts.  Thank you for using our products !
--
-- Disclaimer:  THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY 
--              WHATSOEVER AND XILINX SPECIFICALLY DISCLAIMS ANY 
--              IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
--              A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
--
-- Revision:
--              May 8, 2002     Release
--
-- Other modules instanced in this design:
--          none
--
--------------------------------------------------------------------------------
-- 
-- This module demultiplexes ANC packets from the video stream. Up to four
-- different types of packets may be searched for and demultiplexed. Packets
-- that have been demultiplexed may optionally be marked for deletion in the
-- video stream.
-- 
-- This module is instanced by the anc_demux module to do all the work of packet
-- demultiplexing.
-- 
-- The module allows up to four different ANC packet types to be specified. 
-- There are four sets (a through d) of inputs signals used to find ANC packets 
-- to be demultiplexed. The signals in each set are described below:
-- 
-- did_[a:d]: These eight-bit values are compared against the DID words of all 
-- ANC packets to search for ANC packets to be demultiplexed. If the DID word 
-- indicates a Type 2 packet, the SDID word must also match. For Type 1 packets 
-- the SDID word is ignored.
-- 
-- sdid_[a:d]: These eight-bit values are compared against the SDID words of all
-- Type 2 ANC packets to search for ANC packets to be demultiplexed.
-- 
-- en_[a:d]: Each DID/SDID pair has an associated enable signal. If the enable
-- signal is low, the pair is not used when searching for ANC packets to
-- demultiplex.
-- 
-- del_pkt_[a:d]: Each DID/SDID pair has an associated del_pkt signal. If the
-- del_pkt signal is high, ANC packets matching the DID/SDID pair are marked for
-- deletion in the video stream after they have been demultiplexed.
-- 
-- The demultiplexed packet data comes out the data_out port along with a number
-- of decoded signals indicating what type of data is on the port.
-- 
-- data_out: This 10-bit port carries the demultiplexed ANC packet data. 
-- Actually, this port is quite simply the vid_in port delayed by three clock 
-- cycles.
-- 
-- data_out_valid: This signal indicates when a demultiplexed ANC packet is on
-- the data_out port. This signal becomes asserted when the DID word is on the
-- data_out port and stays asserted through the last word of the ANC packet (CS).
-- This signal is not asserted during the three-word ADF that precedes the ANC
-- packet.
-- 
-- match_code: This 2-bit output port indicates which of the DID/SDID input sets
-- matched the ANC packet that is being demultiplexed to the data_out port: "00"
-- for set A, "01" for set B, "10" for set C, and "11" for set D. This port
-- is valid when data_out_valid signal is asserted high.
-- 
-- did: This signal is asserted when the DID word of a demultiplexed packet is
-- on the data_out port.
-- 
-- sdid: This signal is asserted when the SDID word of a demultiplexed Type 2
-- packet is on the data_out port.
-- 
-- dbn: This signal is asserted when the DBN word of a demultiplexed Type 1
-- packet is on the data_out port.
-- 
-- dc: This signal is asserted when the DC word of a demultiplexed packet is on
-- the data_out port.
-- 
-- udw: This signal is asserted when any UDW word of a demultiplexed packet is
-- on the data_out port.
-- 
-- cs: This signal is asserted when the CS word of a demultiplexed packet is on
-- the data_out port.
-- 
-- The module also has a vid_out port. The data on this port is usually the same
-- as the vid_in port, but delayed by three clock cycles. However, ANC packets
-- can be marked for deletion by the module. Those that get marked for deletion
-- have their DID and CS value modified when they come out the vid_out port.
-- Packets that get marked for deletion by the module appear in their original
-- form on the data_out port.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;

use work.anc_edh_pkg.all;

entity anc_extract is
    port (
        -- inputs
        clk:            in    std_ulogic;   -- clock input
        ce:             in    std_ulogic;   -- clock enable
        rst:            in    std_ulogic;   -- async reset input
        anc_next:       in    std_ulogic;   -- ANC packet begins next word
        vid_in:         in    video_type;   -- video data input
        en_a:           in    std_ulogic;   -- enable for DID A decoder
        did_a:          in    ubyte_type;   -- first DID code to match
        sdid_a:         in    ubyte_type;   -- first SDID code to match
        del_pkt_a:      in    std_ulogic;   -- packet will be deleted if asserted
        en_b:           in    std_ulogic;   -- enable for DID B decoder
        did_b:          in    ubyte_type;   -- second DID code to match
        sdid_b:         in    ubyte_type;   -- second SDID code to match
        del_pkt_b:      in    std_ulogic;   -- packet will be deleted if asserted
        en_c:           in    std_ulogic;   -- enable for DID C decoder
        did_c:          in    ubyte_type;   -- third DID code to match
        sdid_c:         in    ubyte_type;   -- third SDID code to match
        del_pkt_c:      in    std_ulogic;   -- packet will be deleted if asserted
        en_d:           in    std_ulogic;   -- enable for DID D decoder
        did_d:          in    ubyte_type;   -- fourth DID code to match
        sdid_d:         in    ubyte_type;   -- fourth SDID code to match
        del_pkt_d:      in    std_ulogic;   -- packet will be deleted if asserted

        -- outputs
        data_out:       out   video_type;   -- output packet data
        data_out_valid: out   std_ulogic;   -- asserted while all words of a matching packet are on data_out
        match_code:     out                 -- indicates DID/SDID combination matched the current packet
            std_ulogic_vector(1 downto 0);  
        did:            out   std_ulogic;   -- asserted when a DID word from a matching packet is on data_out
        dbn:            out   std_ulogic;   -- asserted when a DBN word from a matching packet is on data_out
        sdid:           out   std_ulogic;   -- asserted when an SDID word from a matching packet is on data_out
        dc:             out   std_ulogic;   -- asserted when a DC word from a matching packet is on data_out
        udw:            out   std_ulogic;   -- asserted when a UDW word from a matching packet is on data_out
        cs:             out   std_ulogic;   -- asserted when a CS word from a matching packet is on data_out
        vid_out:        out   video_type);  -- output video stream
end;

architecture synth of anc_extract is

constant LATENCY :      integer := 3;

-------------------------------------------------------------------------------
-- Subtype definitions
--      
subtype delay     is    -- used to delay 1-bit video timing signals to match latency
            std_ulogic_vector(LATENCY-1 downto 0);

subtype matchcode is    -- code indicating which DID/SDID input pair matched ANC packet
            std_ulogic_vector(1 downto 0);

subtype matchvec  is    -- unary bit version of matchcode
            std_ulogic_vector(3 downto 0);

-------------------------------------------------------------------------------
-- Constant definitions
--      

--
-- This group of constants defines the states of the EDH processor state
-- machine.
--
constant STATE_WIDTH :  integer := 4;

subtype state           is std_ulogic_vector(STATE_WIDTH - 1 downto 0);

constant S_WAIT :       state := "0000";
constant S_ADF1 :       state := "0001";
constant S_ADF2 :       state := "0010";
constant S_ADF3 :       state := "0011";
constant S_DID :        state := "0100";
constant S_SDID :       state := "0101";
constant S_DC :         state := "0110";
constant S_UDW :        state := "0111";
constant S_CS :         state := "1000";


-------------------------------------------------------------------------------
-- Signal definitions
--
signal current_state:   state;          -- FSM current state
signal next_state:      state;          -- FSM next state
signal vid_in_reg:      video_type;     -- video input pipeline reg
signal vid_dly_1:       video_type;     -- video pipeline delay reg
signal vid_dly_2:       video_type;     -- video pipeline delay reg
signal vid_mux:         video_type;     -- output video MUX
signal anc_next_dly:    delay;          -- delay reg for anc_next signal
signal pkt_type:        std_ulogic;     -- 1=type 1 ANC pkt, 0 = type 2
signal pkt_delete:      std_ulogic;     -- asserted if pkt should be deleted
signal ld_udw_cntr:     std_ulogic;     -- loads the UDW counter
signal udw_cntr:        ubyte_type;     -- counts the UDW words in packet
signal udw_cntr_eq_0:   std_ulogic;     -- asserted when UDW counter - 1 = 0
signal udw_cntr_mux:    ubyte_type;     -- input MUX for UDW counter
signal do_delete:       std_ulogic;     -- causes DID to be replaced by deletion code
signal ld_match_code:   std_ulogic;     -- loads the match_code output register
signal check_did:       std_ulogic;     -- controls the comparator input MUXes
signal mux_a:           ubyte_type;     -- cmp_a input mux
signal mux_b:           ubyte_type;     -- cmp_b input mux
signal mux_c:           ubyte_type;     -- cmp_c input mux
signal mux_d:           ubyte_type;     -- cmp_d input mux
signal a_x:             ubyte_type;     -- mux_a output after 8-bit conversion
signal b_x:             ubyte_type;     -- mux_b output after 8-bit conversion
signal c_x:             ubyte_type;     -- mux_c output after 8-bit conversion
signal d_x:             ubyte_type;     -- mux_d output after 8-bit conversion
signal in_x:            ubyte_type;     -- DID or SDID from input video after 8-bit conversion
signal cmp_a:           std_ulogic;     -- compares a_x with in_x
signal cmp_b:           std_ulogic;     -- compares b_x with in_x
signal cmp_c:           std_ulogic;     -- compares c_x with in_x
signal cmp_d:           std_ulogic;     -- compares d_x with in_x
signal did_match:       matchvec;       -- register that holds cmp_[a:d] outputs
signal sdid_match:      matchvec;       -- vector containing SDID comparison results
signal matches:         matchvec;       -- vector indicating did/sdid pair matches
signal encoded_match:   matchcode;      -- priority encoded packet match value
signal match:           std_ulogic;     -- asserted on a packet match
signal set_do_valid:    std_ulogic;     -- sets the data_out_valid signal
signal clr_do_valid:    std_ulogic;     -- clears the data_out_valid signal
signal checksum:        cksum_type;     -- checksum generator
signal clr_checksum:    std_ulogic;     -- clears the checksum generator
signal output_checksum: std_ulogic;     -- checksum is output when asserted
signal did_8_bit_d:     std_ulogic;     -- asserted when DID indicates 8-bit value
signal did_8_bit:       std_ulogic;     -- registered versio of did_8_bit_d
signal eight_bit:       std_ulogic;     -- asserted when DID/SDID pair are 8-bit values
signal ld_pkt_type :    std_ulogic;     -- loads the pkt_type register

begin
    
    --
    -- FSM: current_state register
    --
    -- This code implements the current state register. 
    --
    process(clk, rst)
    begin
        if (rst = '1') then
            current_state <= S_WAIT;
        elsif (clk'event and clk = '1') then
            if (ce = '1') then
                current_state <= next_state;
            end if;
        end if;
    end process;

    --
    -- FSM: next_state logic
    --
    -- This case statement generates the next_state value for the FSM based on
    -- the current_state and the various FSM inputs.
    --
    process(current_state, anc_next_dly(2), match, udw_cntr_eq_0)
    begin
        case current_state is
            when S_WAIT =>  
                if (anc_next_dly(2) = '1') then
                    next_state <= S_ADF1;
                else
                    next_state <= S_WAIT;
                end if;

            when S_ADF1 =>
                next_state <= S_ADF2;

            when S_ADF2 =>
                next_state <= S_ADF3;

            when S_ADF3 =>
                if (match = '1') then
                    next_state <= S_DID;
                else
                    next_state <= S_WAIT;
                end if;

            when S_DID =>
                next_state <= S_SDID;

            when S_SDID =>
                next_state <= S_DC;

            when S_DC =>
                if (udw_cntr_eq_0 = '1') then
                    next_state <= S_CS;
                else
                    next_state <= S_UDW;
                end if;

            when S_UDW =>
                if (udw_cntr_eq_0 = '1') then
                    next_state <= S_CS;
                else
                    next_state <= S_UDW;
                end if;

            when S_CS =>
                if (anc_next_dly(2) = '1') then
                    next_state <= S_ADF1;
                else
                    next_state <= S_WAIT;
                end if;

            when others =>
                next_state <= S_WAIT;
        end case;   
    end process;
                            
    --
    -- FSM: outputs
    --
    -- This block decodes the current state to generate the various outputs of the
    -- FSM.
    --
    process(current_state, pkt_type, pkt_delete, match)
    begin
        -- Unless specifically assigned in the case statement, all FSM outputs
        -- are as defined below.
        do_delete           <= '0';
        set_do_valid        <= '0';
        clr_do_valid        <= '0';
        did                 <= '0';
        sdid                <= '0';
        dbn                 <= '0';
        dc                  <= '0';
        udw                 <= '0';
        cs                  <= '0';
        ld_udw_cntr         <= '0';
        ld_match_code       <= '0';
        clr_checksum        <= '0';
        output_checksum     <= '0';
        check_did           <= '0';
        ld_pkt_type         <= '0';

        case current_state is
            when S_ADF2 =>
                check_did <= '1';
                ld_pkt_type <= '1';