mc8051_core.prj

8051硬核源码（VHDL）

#add_file options
add_file -vhdl -lib work "../../vhdl/mc8051_p.vhd"
add_file -vhdl -lib work "../../vhdl/addsub_core_.vhd"
add_file -vhdl -lib work "../../vhdl/addsub_core_struc.vhd"
add_file -vhdl -lib work "../../vhdl/addsub_cy_.vhd"
add_file -vhdl -lib work "../../vhdl/addsub_cy_rtl.vhd"
add_file -vhdl -lib work "../../vhdl/addsub_ovcy_.vhd"
add_file -vhdl -lib work "../../vhdl/addsub_ovcy_rtl.vhd"
add_file -vhdl -lib work "../../vhdl/alucore_.vhd"
add_file -vhdl -lib work "../../vhdl/alucore_rtl.vhd"
add_file -vhdl -lib work "../../vhdl/alumux_.vhd"
add_file -vhdl -lib work "../../vhdl/alumux_rtl.vhd"
add_file -vhdl -lib work "../../vhdl/comb_divider_.vhd"
add_file -vhdl -lib work "../../vhdl/comb_divider_rtl.vhd"
add_file -vhdl -lib work "../../vhdl/comb_mltplr_.vhd"
add_file -vhdl -lib work "../../vhdl/comb_mltplr_rtl.vhd"
add_file -vhdl -lib work "../../vhdl/control_fsm_.vhd"
add_file -vhdl -lib work "../../vhdl/control_fsm_rtl.vhd"
add_file -vhdl -lib work "../../vhdl/control_mem_.vhd"
add_file -vhdl -lib work "../../vhdl/control_mem_rtl.vhd"
add_file -vhdl -lib work "../../vhdl/dcml_adjust_.vhd"
add_file -vhdl -lib work "../../vhdl/dcml_adjust_rtl.vhd"
add_file -vhdl -lib work "../../vhdl/mc8051_alu_.vhd"
add_file -vhdl -lib work "../../vhdl/mc8051_alu_struc.vhd"
add_file -vhdl -lib work "../../vhdl/mc8051_control_.vhd"
add_file -vhdl -lib work "../../vhdl/mc8051_control_struc.vhd"
add_file -vhdl -lib work "../../vhdl/mc8051_siu_.vhd"
add_file -vhdl -lib work "../../vhdl/mc8051_siu_rtl.vhd"
add_file -vhdl -lib work "../../vhdl/mc8051_siu_rtl_cfg.vhd"
add_file -vhdl -lib work "../../vhdl/mc8051_tmrctr_.vhd"
add_file -vhdl -lib work "../../vhdl/mc8051_tmrctr_rtl.vhd"
add_file -vhdl -lib work "../../vhdl/mc8051_core_.vhd"
add_file -vhdl -lib work "../../vhdl/mc8051_core_struc.vhd"


#implementation: "virtex2p"
impl -add virtex2p

#device options
set_option -technology VIRTEX2P
set_option -part XC2VP7
set_option -package FG456
set_option -speed_grade -7

#compilation/mapping options
set_option -default_enum_encoding default
set_option -symbolic_fsm_compiler 0
set_option -resource_sharing 1
set_option -use_fsm_explorer 0
set_option -top_module "mc8051_core"

#map options
set_option -frequency 50.000
set_option -fanout_limit 10000
set_option -disable_io_insertion 0
set_option -pipe 0
set_option -update_models_cp 0
set_option -verification_mode 0
set_option -fixgatedclocks 0
set_option -modular 0
set_option -retiming 0

#simulation options
set_option -write_verilog 0
set_option -write_vhdl 0

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "virtex2p/mc8051_core.edf"

#implementation attributes
set_option -synthesis_onoff_pragma 0


#implementation: "cyclone"
impl -add cyclone

#device options
set_option -technology CYCLONE
set_option -part EP1C6
set_option -package FC256
set_option -speed_grade -8

#compilation/mapping options
set_option -default_enum_encoding onehot
set_option -symbolic_fsm_compiler 0
set_option -resource_sharing 1
set_option -use_fsm_explorer 0
set_option -top_module "mc8051_core"

#map options
set_option -frequency 50.000
set_option -fanout_limit 500
set_option -disable_io_insertion 0
set_option -pipe 0
set_option -update_models_cp 0
set_option -retiming 0
set_option -fixgatedclocks 0
set_option -verification_mode 0

#simulation options
set_option -write_verilog 0
set_option -write_vhdl 0

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "cyclone/mc8051_core.vqm"

#implementation attributes
set_option -synthesis_onoff_pragma 0


#implementation: "stratixii"
impl -add stratixii

#device options
set_option -technology STRATIXII
set_option -part EP2S15
set_option -package FC484
set_option -speed_grade -5

#compilation/mapping options
set_option -default_enum_encoding onehot
set_option -symbolic_fsm_compiler 0
set_option -resource_sharing 1
set_option -use_fsm_explorer 0
set_option -top_module "mc8051_core"

#map options
set_option -frequency 50.000
set_option -fanout_limit 500
set_option -disable_io_insertion 0
set_option -pipe 0
set_option -update_models_cp 0
set_option -retiming 0
set_option -fixgatedclocks 0
set_option -verification_mode 0

#simulation options
set_option -write_verilog 0
set_option -write_vhdl 0

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "stratixii/mc8051_core.vqm"


#implementation: "virtex4p"
impl -add virtex4p

#device options
set_option -technology VIRTEX4
set_option -part XC4VLX15
set_option -package SF363
set_option -speed_grade -10

#compilation/mapping options
set_option -default_enum_encoding default
set_option -symbolic_fsm_compiler 0
set_option -resource_sharing 1
set_option -use_fsm_explorer 0
set_option -top_module "mc8051_core"

#map options
set_option -frequency 50.000
set_option -fanout_limit 10000
set_option -disable_io_insertion 0
set_option -pipe 0
set_option -update_models_cp 0
set_option -verification_mode 0
set_option -fixgatedclocks 0
set_option -modular 0
set_option -retiming 0

#simulation options
set_option -write_verilog 0
set_option -write_vhdl 0

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "virtex4/mc8051_core.edf"
impl -active "virtex2p"