mc8051.sdc

8051硬核源码（VHDL）

#################
# Attributes
#################

##################
# Clocks
##################
create_clock  -domain Design_Clock -name Design_Clock -period 50.000000 -waveform { 0.000000 25.000000 }
create_clock { clk } -domain ClockDomain0 -name clk -period 50.000000 -waveform { 0.000000 25.000000 }

##################
# Input delays
##################
set_input_delay 10 -clock clk -add_delay { p0_i* }
set_input_delay 10 -clock clk -add_delay { p1_i* }
set_input_delay 10 -clock clk -add_delay { p2_i* }
set_input_delay 10 -clock clk -add_delay { p3_i* }
set_input_delay 10 -clock clk -add_delay { ram_data_i* }
set_input_delay 10 -clock clk -add_delay { rom_data_i* }

###################
# Output delays
###################
set_output_delay 10 -clock clk -add_delay { p0_o* }
set_output_delay 10 -clock clk -add_delay { p1_o* }
set_output_delay 10 -clock clk -add_delay { p2_o* }
set_output_delay 10 -clock clk -add_delay { p3_o* }

###########################
# False Paths / Multicycles
###########################
#set_multicycle_path 2 -from { i_mc8051_alu/gen_multiplier_i_comb_mltplr/mltplcnd_i* }
#set_multicycle_path 2 -from { i_mc8051_alu/gen_multiplier_i_comb_mltplr/mltplctr_i* }