synthesize.tcl

8051硬核源码（VHDL）

remove_design -all
setup_design -design="mc8051_core"
setup_design -arch="struc"
add_input_file -format {VHDL} -work work {../../vhdl/mc8051_p.vhd}
add_input_file -format {VHDL} -work work {../../vhdl/addsub_cy_.vhd}
add_input_file -format {VHDL} -work work {../../vhdl/addsub_cy_rtl.vhd}
add_input_file -format {VHDL} -work work {../../vhdl/addsub_ovcy_.vhd}
add_input_file -format {VHDL} -work work {../../vhdl/addsub_ovcy_rtl.vhd}
add_input_file -format {VHDL} -work work {../../vhdl/addsub_core_.vhd}
add_input_file -format {VHDL} -work work {../../vhdl/addsub_core_struc.vhd}
add_input_file -format {VHDL} -work work {../../vhdl/alumux_.vhd}
add_input_file -format {VHDL} -work work {../../vhdl/alumux_rtl.vhd}
add_input_file -format {VHDL} -work work {../../vhdl/comb_divider_.vhd}
add_input_file -format {VHDL} -work work {../../vhdl/comb_divider_rtl.vhd}
add_input_file -format {VHDL} -work work {../../vhdl/comb_mltplr_.vhd}
add_input_file -format {VHDL} -work work {../../vhdl/comb_mltplr_rtl.vhd}
add_input_file -format {VHDL} -work work {../../vhdl/control_fsm_.vhd}
add_input_file -format {VHDL} -work work {../../vhdl/control_fsm_rtl.vhd}
add_input_file -format {VHDL} -work work {../../vhdl/control_mem_.vhd}
add_input_file -format {VHDL} -work work {../../vhdl/control_mem_rtl.vhd}
add_input_file -format {VHDL} -work work {../../vhdl/dcml_adjust_.vhd}
add_input_file -format {VHDL} -work work {../../vhdl/dcml_adjust_rtl.vhd}
add_input_file -format {VHDL} -work work {../../vhdl/alucore_.vhd}
add_input_file -format {VHDL} -work work {../../vhdl/alucore_rtl.vhd}
add_input_file -format {VHDL} -work work {../../vhdl/mc8051_alu_.vhd}
add_input_file -format {VHDL} -work work {../../vhdl/mc8051_alu_struc.vhd}
add_input_file -format {VHDL} -work work {../../vhdl/mc8051_siu_.vhd}
add_input_file -format {VHDL} -work work {../../vhdl/mc8051_siu_rtl.vhd}
add_input_file -format {VHDL} -work work {../../vhdl/mc8051_tmrctr_.vhd}
add_input_file -format {VHDL} -work work {../../vhdl/mc8051_tmrctr_rtl.vhd}
add_input_file -format {VHDL} -work work {../../vhdl/mc8051_control_.vhd}
add_input_file -format {VHDL} -work work {../../vhdl/mc8051_control_struc.vhd}
add_input_file -format {VHDL} -work work {../../vhdl/mc8051_core_.vhd}
add_input_file -format {VHDL} -work work {../../vhdl/mc8051_core_struc.vhd}
add_input_file -format {Synopsys Design Constraints} -work work {mc8051.sdc}
setup_design -basename="mc8051_core"
setup_design -manufacturer "Xilinx" -family "VIRTEX-E" -part "v400ebg432" -speed "8" -package ""
setup_design -addio
setup_design -vhdl=false
setup_design -verilog=false
setup_design -edif
setup_design -vendor_constraint_file
setup_design -transformations
setup_design -retiming=false
setup_design -advanced_fsm_optimization
setup_design -resource_sharing
setup_design -fault_tolerant=false
setup_design -frequency 20
setup_design -input_delay 10
setup_design -output_delay 10
setup_design -search_path {precision}
compile
synthesize
report_area area.txt -hierarchy -all_leafs
report_timing timing.txt -show_nets -cell_names -summary -clock_frequency