pulse_width_detector_filter.vhd

通信控制中常用的脉冲宽度检测程序

--****************脉宽检测程序***************************

----------------------TOP----------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;

entity pulse_width_detector_filter is
	port(
			clk: in std_logic;
			pulse_in: in std_logic;
			valid_pulse_rising_edge: out std_logic;
			valid_pulse_width:out integer
		);
end pulse_width_detector_filter;


architecture pulse_width_detector_filter_body of pulse_width_detector_filter is
	component pulse_counter is	--component(1)脉宽计算模块
	port(
			clk: in std_logic;
			pulse_in: in std_logic;
			pulse_width: out integer
		);
	end component;
	
	component dff_deliver is	--component(2)脉宽寄存传输模块(相当于dff的功能)
	port
		(
			dff_clk: in std_logic;
			D_pulse_width: in integer;
			Q_pulse_width: out integer
		);
	end component;
	
	component output_logic is	--component(3)脉宽判断及输出逻辑模块
	port
		(
			clk: in std_logic;
			pulse_in: in std_logic;
			pulse_width: in integer;
			valid_pulse_rising_edge: out std_logic;
			valid_pulse_width:out integer
		);
	end component;
	
	--连接信号
	signal pulse_width_wire1: integer;
	signal pulse_width_wire2: integer;
	signal dff_clk_wire: std_logic;
	
begin
	U1:pulse_counter port map( clk, pulse_in, pulse_width_wire1  );--component(1)
	U2:dff_deliver port map( dff_clk_wire, pulse_width_wire1, pulse_width_wire2  );--component(2)
	U3:output_logic port map( clk, pulse_in, pulse_width_wire2, valid_pulse_rising_edge, valid_pulse_width );--component(3)
	
	dff_clk_wire<=not pulse_in;  --输入信号pulse_in的下降沿就是寄存器的上升沿
	
end pulse_width_detector_filter_body;
--------------------------------------------------------



------------------------component(1)--------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;

entity pulse_counter is
	port(
			clk: in std_logic;
			pulse_in: in std_logic;
			pulse_width: out integer
		);
end pulse_counter;


architecture pulse_counter_body of pulse_counter is
	signal count:integer;
begin
	process(clk)
	begin
		if clk='1' and clk'event then
			if pulse_in='0' then
				count<=0;			--当pulse_in为0时,计数完毕并将计数器复位
			else
				count<=count+1;		--当pulse_in为1时,开始计算pulse_in的脉冲宽度
			end if;					--因为clk较有效pulse_in快很多,所以误差小,不需要判断pulse_in的上下降沿
		end if;
		
		pulse_width<=count;
	end process;
end pulse_counter_body;
--------------------------------------------------------


-------------------------component(2)-------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;

entity dff_deliver is
	port
		(
			dff_clk: in std_logic;
			D_pulse_width: in integer;
			Q_pulse_width: out integer
		);
end dff_deliver;

architecture dff_deliver_body of dff_deliver is
begin
	process(dff_clk)
	begin
		if dff_clk='1' and dff_clk'event then	--仅当pulse_in下降沿,也就是脉宽计数完毕后,
			Q_pulse_width<=D_pulse_width;		--才将新的脉宽值从寄存器Q端打出
		end if;
	end process;
end dff_deliver_body;
--------------------------------------------------------



------------------------component(3)--------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;

entity output_logic is
	generic (valid_width:integer:=5);	--定义合理脉宽的判断标准,低于该标准的脉宽信号即视为不合理的毛刺,将被忽略
	port
		(
			clk: in std_logic;
			pulse_in: in std_logic;
			pulse_width: in integer;
			valid_pulse_rising_edge: out std_logic;	--输出有效上升沿,表征输入脉冲信号合理,非毛刺
			valid_pulse_width:out integer	--输出当前输入脉冲信号的脉宽值
		);
end output_logic;

architecture output_logic_body of output_logic is
	signal temp:integer;
	signal width:integer;
	signal Y:std_logic;
begin
	process(clk,pulse_in,pulse_width)
	begin
		if clk='1' and clk'event then
			if pulse_in='1' then	--给输出逻辑中的计数器赋初值
				temp<=4;			--如果当前输出逻辑正在运行,则该语句的赋值不会影响计数器temp的值,将被输出逻辑中的赋值语句所覆盖
			elsif pulse_in='0' then
				if pulse_width>=valid_width then	--根据脉宽判断当前输入信号是否合理
					width<=pulse_width;	--如果合理,则将脉宽值保存起来,以免被毛刺带来的新脉宽值破坏
				end if;
			end if;
			
			if width>=valid_width then	--如果合理,则开始执行输出逻辑,产生有效上升沿
				if temp>=1 and temp<=4 then
					temp<=temp-1;
					Y<='1';
				else
					Y<='0';
					width<=0;
				end if;
			end if;
		end if;
		
		valid_pulse_rising_edge<=Y;	--输出有效上升沿,表征输入脉冲信号合理,非毛刺
		valid_pulse_width<=width;	--输出当前输入脉冲信号的脉宽值
		
	end process;
end output_logic_body;
---------------------------------------------------------